View AD9548PCBZ_3657566.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

quad/octal input network clock generator/synchronizer ad9548 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2009 analog devices, inc. all rights reserved. features supports stratum 2 stability in holdover mode supports reference switchover with phase build-out supports hitless reference switchover auto/manual holdover and reference switchover 4 pairs of reference input pins with each pair configurable as a single differential input or as 2 independent single- ended inputs input reference frequencies from 1 hz to 750 mhz reference validation and frequency monitoring (1 ppm) programmable input reference switchover priority 30-bit programmable input reference divider 4 pairs of clock output pins with each pair configurable as a single differential lvds/lvpecl output or as 2 single- ended cmos outputs output frequencies up to 450 mhz 30-bit integer and 10-bit fractional programmable feedback divider programmable digital loop filter covering loop bandwidths from 0.001 hz to 100 khz optional low noise lc-vco system clock multiplier optional crystal resonator for system clock input on-chip eeprom to store multiple power-up profiles software controlled power-down 88-lead lfcsp package applications network synchronization cleanup of reference clock jitter gps 1 pulse per second synchronization sonet/sdh clocks up to oc-192, including fec stratum 2 holdover, jitter cleanup, and phase transient control stratum 3e and stratum 3 reference clocks wireless base station controllers cable infrastructure data communications general description the ad9548 provides synchronization for many systems, including synchronous optical networks (sonet/sdh). the ad9548 generates an output clock synchronized to one of up to four differential or eight single-ended external input references. the digital pll allows for reduction of input time jitter or phase noise associated with the external references. the ad9548 continuously generates a clean (low jitter), valid output clock even when all references have failed by means of a digitally controlled loop and holdover circuitry. the ad9548 operates over an industrial temperature range of ?40c to +85c. functional block diagram reference inputs and monitor mux status and control pins serial control interface (spi or i 2 c) eeprom digital pll clock distribution sync dac clock multiplier stable source analog filter ad9548 channel 0 divider channel 1 divider channel 2 divider channel 3 divider 08022-001 figure 1.
ad9548 rev. 0 | page 2 of 112 table of contents features .............................................................................................. 1 ? applications ....................................................................................... 1 ? general description ......................................................................... 1 ? functional block diagram .............................................................. 1 ? revision history ............................................................................... 3 ? specifications ..................................................................................... 4 ? supply voltage ............................................................................... 4 ? supply current .............................................................................. 4 ? power dissipation ......................................................................... 4 ? logic inputs (m7 to m0, reset, tdi, tclk, tms) .............. 5 ? logic outputs (m7 to m0, irq, tdo) ..................................... 5 ? system clock inputs (sysclkp/sysclkn) ........................... 5 ? distribution clock inputs (clkinp/clkinn) ...................... 6 ? reference inputs (refa/refaa to refd/refdd) .............. 7 ? reference monitors ...................................................................... 7 ? reference switchover specifications .......................................... 8 ? distribution clock outputs (out0 to out3) ........................ 8 ? dac output characteristics (dacoutp/dacoutn) ....... 9 ? time duration of digital functions ........................................ 10 ? digital pll .................................................................................. 10 ? digital pll lock detection ...................................................... 10 ? holdover specifications ............................................................. 10 ? serial port specificationsspi mode ...................................... 11 ? serial port specificationsi 2 c mode ...................................... 11 ? jitter generation ......................................................................... 12 ? absolute maximum ratings .......................................................... 14 ? esd caution ................................................................................ 14 ? pin configuration and function descriptions ........................... 15 ? typical performance characteristics ........................................... 18 ? input/output termination recommendations .......................... 23 ? getting started ................................................................................ 24 ? power-on reset .......................................................................... 24 ? initial pin programming ........................................................... 24 ? device register programming .................................................. 24 ? theory of operation ...................................................................... 26 ? overview ...................................................................................... 26 ? reference clock inputs .............................................................. 27 ? reference monitors .................................................................... 27 ? reference profiles ....................................................................... 28 ? reference switchover ................................................................. 30 ? digital pll (dpll) core .......................................................... 32 ? direct digital synthesizer ......................................................... 34 ? tuning word processing ........................................................... 35 ? loop control state machine ..................................................... 36 ? system clock inputs ................................................................... 37 ? sysclk pll multiplier ............................................................. 38 ? clock distribution ..................................................................... 39 ? status and control .......................................................................... 44 ? multifunction pins (m0 to m7) ............................................... 44 ? irq pin ........................................................................................ 45 ? watchdog timer ......................................................................... 46 ? eeprom ..................................................................................... 46 ? serial control port ......................................................................... 51 ? spi/i2c port selection ................................................................ 51 ? spi serial port operation .......................................................... 51 ? i2c serial port operation .......................................................... 55 ? i/o programming registers .......................................................... 58 ? buffered/active registers .......................................................... 58 ? autoclear registers ..................................................................... 58 ? register access restrictions ...................................................... 59 ? register map ................................................................................... 60 ? register map bit descriptions ...................................................... 70 ? serial port configuration (register 0000 to register 0005) ............................................................................. 70 ? system clock (register 0100 to register 0108) ...................... 71 ? general configuration (register 0200 to register 0214) ..... 72 ? dpll configuration (register 0300 to register 031b)......... 75 ? clock distribution output configuration (register 0400 to register 0419) ............................................................................. 77 ? reference input configuration (register 0500 to register 0507) ............................................................................................. 81 ? profile registers (register 0600 to register 07ff) ................ 83 ? operational controls (register 0a00 to register 0a10) ...... 92 ? status readback (register 0d00 to register 0d19) ............... 97 ? nonvolatile memory (eeprom) control (register 0e00 to register 0e03) ........................................................................... 100 ? eeprom storage sequence (register 0e10 to register 0e3f) ........................................................................... 101 ? power supply partitions ............................................................... 105 ? 3.3 v supplies ............................................................................ 105 ? 1.8 v supplies ............................................................................ 105 ?
ad9548 rev. 0 | page 3 of 112 thermal performance .................................................................. 106 ? calculating digital filter coefficients ....................................... 107 ? calculation of the register values ..................................... 108 ? calculation of the register values ...................................... 108 ? calculation of the register values ....................................... 109 ? calculation of the register values ....................................... 109 ? outline dimensions ...................................................................... 110 ? ordering guide ......................................................................... 110 ? revision history 5 /09revision 0: initial version
ad9548 rev. 0 | page 4 of 112 specifications minimum (min) and maximum (max) values apply for the full range of supply voltage and operating temperature variations. typical (typ) values apply for avdd3 = dvdd_i/o = 3.3 v; avdd = dvdd = 1.8 v; t a = 25c; i dac = 20 ma (full scale), unless otherwise noted. supply voltage table 1. parameter min typ max unit test conditions/comments supply voltage dvdd3 3.135 3.30 3.465 v pin 7, pin 82 dvdd 1.71 1.80 1.89 v pin 1, pin 6, pin 12, pin 14, pin 15, pin 77, pin 83, pin 88 avdd3 3.135 3.30 3.465 v pin 21, pin 22, pin 47, pin 60, pin 66, pin 67, pin 73 3.3 v supply (typical) 3.135 3.30 3.465 v pin 31, pin 37, pin 38, pin 44 1.8 v supply (alternative) 1.71 1.80 1.89 v pin 31, pin 37, pin 38, pin 44 avdd 1.71 1.80 1.89 v pin 23, pin 24, pin 29, pin 34, pin 41, pin 50, pin 55, pin 59, pin 63, pin 70, pin 74 supply current the test conditions for the maximum (max) supply current are the same as the test conditions for the all blocks running paramet er of table 3 . the test conditions for the typical (typ) supply current are the same as the test conditions for the typical configuration para meter of table 3 . table 2. parameter min typ max unit test conditions/comments supply current i dvdd3 1.5 3 ma pin 7, pin 82 i dvdd 190 215 ma pin 1, pin 6, pin 12, pin 14, pin 15, pin 77, pin 83, pin 88 i avdd3 52 75 ma pin 21, pin 22, pin 47, pin 60, pin 66, pin 67, pin 73 i avdd3 3.3 v supply (typical) 24 110 ma pin 31, pin 37, pin 38, pin 44 1.8 v supply (alternative) 24 110 ma pin 31, pin 37, pin 38, pin 44 i avdd 135 163 ma pin 23, pin 24, pin 29, pin 34, pin 41, pin 50, pin 55, pin 59, pin 63, pin 70, pin 74 power dissipation table 3. parameter min typ max unit test conditions/comments power dissipation typical configuration 800 1100 mw f sysclk = 20 mhz 1 ; f s = 1 ghz 2 ; f dds = 122.88 mhz 3 ; one lvpecl clock distribution output running at 122.88 mhz (all others powered down); one input reference running at 100 mhz (all others powered down) all blocks running 900 1400 mw f sysclk = 20 mhz 1 ; f s = 1 ghz 2 ; f dds = 399 mhz 3 ; all clock distribution outputs configured as lvpecl at 399 mhz; all input references configured as differential at 100 mhz; fractional-n active (r = 10, s = 39, u = 9, v = 10) full power-down 13 mw conditions = typical configuration; no external pull-up or pull-down resistors
ad9548 rev. 0 | page 5 of 112 parameter min typ max unit test conditions/comments incremental power dissipation conditions = typical configuration; table values show the change in power due to the indicated operation. sysclk pll off ?105 mw f sysclk = 1 ghz 1 ; high frequency direct input mode. input reference on differential 7 mw single-ended 13 mw output distribution driver on lvds 70 mw lvpecl 75 mw cmos 65 mw a single 3.3 v cmos output with a 10 pf load. 1 f sysclk is the frequency at the sysclkp and sysclkn pins. 2 f s is the sample rate of the output dac. 3 f dds is the output frequency of the dds. logic inputs (m7 to m0, reset, tdi, tclk, tms) table 4. parameter min typ max unit test conditions/comments logic inputs (m7 to m0, reset, tdi, tclk, tms) input high voltage (v ih ) 2.1 v input low voltage (v il ) 0.8 v input current (i inh , i inl ) 80 200 a input capacitance (c in ) 3 pf logic outputs (m7 to m0, irq, tdo) table 5. parameter min typ max unit test conditions/comments logic outputs (m7 to m0, irq, tdo) output high voltage (v oh ) 2.7 v i oh = 1 ma output low voltage (v ol ) 0.4 v i ol = 1 ma irq leakage current open-drain mode active low output mode 1 a v oh = 3.3 v active high output mode 1 a v ol =-0 v system clock inputs (sysclkp/sysclkn) table 6. parameter min typ max unit test conditions/comments system clock pll bypassed input frequency range 500 1000 mhz minimum input slew rate 1000 v/s minimum limit imposed for jitter performance duty cycle 40 60 % common-mode voltage 1.2 v internally generated differential input voltage sensitivity 100 mv p-p minimum voltage across pins required to ensure switching between logic states; the instantaneous voltage on either pin must not exceed the supply rails; can accommodate single-ended input by ac grounding unused input input capacitance 2 pf single-ended, each pin input resistance 2.5 k
ad9548 rev. 0 | page 6 of 112 parameter min typ max unit test conditions/comments system clock pll enabled pll output frequency range 900 1000 mhz phase-frequency detector (pfd) rate 150 mhz frequency multiplication range 6 255 a ssumes valid system clock and pfd rates vco gain 70 mhz/v high frequency path input frequency range 100.1 500 mhz minimum input slew rate 200 v/s minimum limit imposed for jitter performance frequency divider range 1 8 binary steps (m = 1, 2, 4, 8) common-mode voltage 1 v internally generated differential input voltage sensitivity 100 mv p-p minimum voltage across pins required to ensure switching between logic states; the instantaneous voltage on either pin must not exceed the supply rails; can accommodate single-ended input by ac grounding unused input input capacitance 3 pf single-ended, each pin input resistance 2.5 k low frequency path input frequency range 3.5 100 mhz minimum input slew rate 50 v/s minimum limit imposed for jitter performance common-mode voltage 1.2 v internally generated differential input voltage sensitivity 100 mv p-p minimum voltage across pins required to ensure switching between logic states; the instantaneous voltage on either pin must not exceed the supply rails; can accommodate single-ended input by ac grounding unused input input capacitance 3 pf single-ended, each pin input resistance 4 k crystal resonator path crystal resonator frequency range 10 50 mhz fundamental mode, at cut maximum crystal motional resistance 100 see the system clock inputs section for recommendations distribution clock inputs (clkinp/clkinn) table 7. parameter min typ max unit test conditions/comments distribution clock inputs (clkinp/clkinn) input frequency range 62.5 500 mhz minimum slew rate 75 v/s minimum limit imposed for jitter performance. common-mode voltage 700 mv internally generated. differential input voltage sensitivity 100 mv p-p capacitive coupling required; can accommodate single-ended input by ac grounding unused input; the instantaneous voltage on either pin must not exceed the supply rails. differential input power sensitivity ?15 dbm the same as voltage sensitivity but specified as power into a 50 load. input capacitance 3 pf input resistance 5 k each pin has a 2.5 k internal dc- bias resistance.
ad9548 rev. 0 | page 7 of 112 reference inputs (refa/refaa to refd/refdd) table 8. parameter min typ max unit test conditions/comments differential operation frequency range sinusoidal input 10 750 mhz lvpecl input 1 750 10 6 hz lvds input 1 750 10 6 hz minimum input slew rate 40 v/s minimum limit imposed for jitter performance common-mode input voltage 2 v internally generated differential input voltage sensitivity 65 mv minimum differential voltage across pins required to ensure switching between logic levels; the instantaneous voltage on either pin must not exceed the supply rails input resistance 25 k input capacitance 3 pf minimum pulse width high 620 ps minimum pulse width low 620 ps single-ended operation frequency range (cmos) 1 250 10 6 hz minimum input slew rate 40 v/s minimum limit imposed for jitter performance input voltage high (v ih ) 1.2 v to 1.5 v threshold setting 0.9 v 1.8 v to 2.5 v threshold setting 1.2 v 3.0 v to 3.3 v threshold setting 1.9 v input voltage low (v il ) 1.2 v to 1.5 v threshold setting 0.27 v 1.8 v to 2.5 v threshold setting 0.5 v 3.0 v to 3.3 v threshold setting 1.0 v input resistance 45 k input capacitance 3 pf minimum pulse width high 1.5 ns minimum pulse width low 1.5 ns reference monitors table 9. parameter min typ max unit test conditions/comments reference monitors reference monitor loss of reference detection time 1.2 sec calculated using the nominal phase detector period (npdp = r/f ref ) 1 frequency out-of range limits 9.54 10 ?7 0.1 f/f ref programmable (lower bound subject to quality of sysclk) validation timer 0.001 65.535 sec programmable in 1 ms increments redetect timer 0.001 65.535 sec programmable in 1 ms increments 1 f ref is the frequency of the active reference; r is the frequency division factor determined by the r-divider.
ad9548 rev. 0 | page 8 of 112 reference switchover specifications table 10. parameter min typ max unit test conditions/comments reference switchover specifications maximum output phase perturbation (phase build-out switchover) 40 200 ps assumes a jitter-free reference; satisfies telcordia gr-1244-core requirements maximum time/time slope (hitless switchover) 315 65,535 ns/sec minimum/maximum values are programmable upper bounds; a minimum value ensures <10% error; satisfies telcordia gr-1244-core requirements time required to switch to a new reference hitless switchover 5 sec calculated using the nominal phase detector period (npdp = r/f ref ) 1 phase build-out switchover 3 sec calculated using the nominal phase detector period (npdp = r/f ref ) 1 1 f ref is the frequency of the active reference; r is the frequency division factor determined by the r-divider. distribution clock outputs (out0 to out3) table 11. parameter min typ max unit test conditions/comments lvpecl mode using internal current setting resistor maximum output frequency 725 mhz rise/fall time (20% to 80%) 180 315 ps 100 termination across output pins duty cycle 45 55 % differential output voltage swing 630 770 910 mv magnitude of voltage across pins; output driver static common-mode output voltage avdd3 ? 1.5 avdd3 ? 1.3 avdd3 ? 1.05 v output driver static lvds mode using internal current setting resistor (nominal 3.12 k) maximum output frequency 725 mhz rise/fall time 1 (20% to 80%) 200 350 ps 100 termination across the output pair duty cycle 40 60 % differential output voltage swing balanced, v od 247 454 mv voltage swing between output pins; output driver static unbalanced, v od 50 mv absolute difference between voltage swing of normal pin and inverted pin; output driver static offset voltage common-mode, v os 1.125 1.375 v output driver static common-mode difference, v os 50 mv voltage difference between pins; output driver static short-circuit output current 13 24 ma output driver static cmos mode weak drive option not supported for operating the cmos drivers using a 1.8 v supply maximum output frequency 3.3 v supply 10 pf load strong drive strength setting 250 mhz weak drive strength setting 25 mhz 1.8 v supply 150 mhz
ad9548 rev. 0 | page 9 of 112 parameter min typ max unit test conditions/comments rise/fall time 1 (20% to 80%) 10 pf load 3.3 v supply strong drive strength setting 0.5 2 ns weak drive strength setting 8 14.5 ns 1.8 v supply 1.5 2.5 ns duty cycle 40 60 % 10 pf load output voltage high (v oh ) output driver static; strong drive strength setting avdd3 = 3.3 v, i oh = 10 ma 2.6 v avdd3 = 3.3 v, i oh = 1 ma 2.9 v avdd3 = 1.8 v, i oh = 1 ma 1.5 v output voltage low (v ol ) output driver static; strong drive strength setting avdd3 = 3.3 v, i ol = 10 ma 0.3 v avdd3 = 3.3 v, i ol = 1 ma 0.1 v avdd3 = 1.8 v, i ol = 1 ma 0.1 v output timing skew 10 pf load between lvpecl outputs 14 125 ps rising edge only; any divide value between lvds outputs 13 138 ps rising edge only; any divide value between cmos 3.3 v outputs strong drive strength setting 23 240 ps weak drive strength setting 24 ps between cmos 1.8 v outputs 40 ps weak drive not supported at 1.8 v between lvpecl outputs and lvds outputs 14 140 ps between lvpecl outputs and cmos outputs 19 ps zero-delay timing skew 5 ns output relative to active input reference; output distribution synchronization to active reference feature enabled; assumes manual phase offset compensation of deterministic latency 1 the listed values are for the slower edge (rise or fall). dac output characteristics (dacoutp/dacoutn) table 12. parameter min typ max unit test conditions/comments dac output characteristics (dacoutp/dacoutn) frequency range 62.5 450 mhz output offset voltage 15 mv this is the single-ended voltage at either dac output pin (no external load) when the internal dac code implies that no current is delivered to that pin. voltage compliance range vss ? 0.5 0.5 vss + 0.5 v output resistance 50 single-ended, each pin has an internal 50 termination to vss. output capacitance 5 pf full-scale output current 20 ma programmable (8 ma to 31 ma; see the dac output section). gain error ?12 +12 % fs
ad9548 rev. 0 | page 10 of 112 time duration of digital functions table 13. parameter min typ max unit test conditions/comments time duration of digital functions eeprom-to-register download time 25 ms using default eeprom storage sequence (see register 0e10 to register 0e3f) register-to-eeprom upload time 200 ms using default eeprom storage sequence (see register 0e10 to register 0e3f minimum power-down exit time 10.5 s dependent on loop-filter bandwidth maximum time from assertion of the reset pin to the m0 to m7 pins entering high impedance state 45 ns digital pll table 14. parameter min typ max unit test conditions/comments digital pll phase-frequency detector (pfd) input frequency range 1 10 7 hz maximum f pfd 1 : f s /100 2 loop bandwidth 0.001 10 5 hz programmable design parameter; maximum f loop = f ref /(20r) 3 phase margin 30 89 degrees programmable design parameter reference input (r) division factor 1 2 30 1, 2, , 1,073,741,824 integer feedback (s) division factor 8 2 30 8, 9, , 1,073,741,824 fractional feedback divide ratio 0 0.999 maximum value: 1022/1023. 1 f pfd is the frequency at the input to the phase-frequency detector. 2 f s is the sample rate of the output dac. 3 f ref is the frequency of the active reference; r is the frequency division factor determined by the r-divider. digital pll lock detection table 15. parameter min typ max unit test conditions/comments phase lock detector threshold programming range 0.001 65.5 ns threshold resolution 1 ps frequency lock detector threshold programming range 0.001 16,700 ns reference-to-feedback period difference threshold resolution 1 ps holdover specifications table 16. parameter min typ max unit test conditions/comments holdover specifications frequency accuracy <0.01 ppm excludes frequency drift of sysclk source; excludes frequency drift of input reference prior to entering holdover
ad9548 rev. 0 | page 11 of 112 serial port specificationsspi mode table 17. parameter min typ max unit test conditions/comments cs internal 30 k pull-up resistor input logic 1 voltage 2.0 v input logic 0 voltage 0.8 v input logic 1 current 30 a input logic 0 current 110 a input capacitance 2 pf sclk internal 30 k pull-down resistor input logic 1 voltage 2.0 v input logic 0 voltage 0.8 v input logic 1 current 1 a input logic 0 current 1 a input capacitance 2 pf sdio as an input input logic 1 voltage 2.0 v input logic 0 voltage 0.8 v input logic 1 current 1 a input logic 0 current 1 a input capacitance 2 pf as an output output logic 1 voltage 2.7 v 1 ma load current output logic 0 voltage 0.4 v 1 ma load current sdo output logic 1 voltage 2.7 v 1 ma load current output logic 0 voltage 0.4 v 1 ma load current timing sclk clock rate, 1/t clk 40 mhz pulse width high, t hi 8 ns pulse width low, t lo 12 ns sdio to sclk setup, t ds 3 ns sclk to sdio hold, t dh 0 ns sclk to valid sdio and sdo, t dv 14 ns cs to sclk setup (t s ) 10 ns cs to sclk hold (t c ) 0 ns cs minimum pulse width high 6 ns serial port specificationsi 2 c mode table 18. parameter min typ max unit test conditions/comments sda, scl (as input) no internal pull-up/down resistor. input logic 1 voltage 0.7 dvdd3 v input logic 0 voltage 0.3 dvdd3 v input current ?10 +10 a for v in = 10% to 90% dvdd3 hysteresis of schmitt trigger inputs 0.015 dvdd3 pulse width of spikes that must be suppressed by the input filter, t sp 50 ns
ad9548 rev. 0 | page 12 of 112 parameter min typ max unit test conditions/comments sda (as output) output logic 0 voltage 0.4 v i o = 3 ma. output fall time from v ihmin to v ilmax 20 + 0.1 c b 1 250 ns 10 pf c b 400 pf. timing scl clock rate 400 khz bus-free time between a stop and start condition, t buf 1.3 s repeated start condition setup time, t su; sta 0.6 s repeated hold time start condition, t hd; sta 0.6 s after this period, the first clock pulse is generated. stop condition setup time, t su; sto 0.6 s low period of the scl clock, t lo 1.3 s high period of the scl clock, t hi 0.6 s scl/sda rise time, t r 20 + 0.1 c b 1 300 ns scl/sda fall time, t f 20 + 0.1 c b 1 300 ns data setup time, t su; dat 100 ns data hold time, t hd; dat 100 ns capacitive load for each bus line, c b 1 400 pf 1 c b is the capacitance (pf) of a single bus line. jitter generation table 19. parameter min typ max unit test conditions/comments jitter generation f ref = 1 hz 1 ; f dds = 122.88 mhz 2 ; f loop = 0.01 hz 3 f sysclk = 20 mhz 4 ocxo; f s = 1 ghz 5 ; q- divider = 1; default sysclk pll charge pump current; results valid for lvpecl, lvds, and cmos output logic types bandwidth: 100 hz to 61 mhz 0.81 ps rms random jitter bandwidth: 5 khz to 20 mhz 0.73 ps rms random jitter bandwidth: 20 khz to 80 mhz 0.79 ps rms random jitter bandwidth: 50 khz to 80 mhz 0.78 ps rms random jitter bandwidth: 4 mhz to 80 mhz 0.37 ps rms random jitter f ref = 8 khz 1 ; f dds = 155.52 mhz 2 ; f loop = 100 hz 3 f sysclk = 50 mhz 4 crystal; f s = 1 ghz 5 ; q-divider = 1; default sysclk pll charge pump current; results valid for lvpecl, lvds, and cmos output logic types bandwidth: 100 hz to 77 mhz 0.71 ps rms random jitter bandwidth: 5 khz to 20 mhz 0.34 ps rms random jitter bandwidth: 20 khz to 80 mhz 0.43 ps rms random jitter bandwidth: 50 khz to 80 mhz 0.43 ps rms random jitter bandwidth: 4 mhz to 80 mhz 0.31 ps rms random jitter f ref = 19.44 mhz 1 ; f dds = 155.52 mhz 2 ; f loop = 1 khz 3 f sysclk = 50 mhz 4 crystal; f s = 1 ghz 5 ; q-divider = 1; default sysclk pll charge pump current; results valid for lvpecl, lvds, and cmos output logic types bandwidth: 100 hz to 77 mhz 1.05 ps rms random jitter bandwidth: 5 khz to 20 mhz 0.34 ps rms random jitter bandwidth: 20 khz to 80 mhz 0.43 ps rms random jitter bandwidth: 50 khz to 80 mhz 0.43 ps rms random jitter bandwidth: 4 mhz to 80 mhz 0.32 ps rms random jitter
ad9548 rev. 0 | page 13 of 112 parameter min typ max unit test conditions/comments f ref = 19.44 hz 1 ; f dds = 311.04 mhz 2 ; f loop = 1 khz 3 f sysclk = 50 mhz 4 crystal; f s = 1 ghz 5 ; q-divider = 1; default sysclk pll charge pump current; results valid for lvpecl, lvds, and cmos output logic types bandwidth: 100 hz to 100 mhz 0.67 ps rms random jitter bandwidth: 5 khz to 20 mhz 0.31 ps rms random jitter bandwidth: 20 khz to 80 mhz 0.33 ps rms random jitter bandwidth: 50 khz to 80 mhz 0.33 ps rms random jitter bandwidth: 4 mhz to 80 mhz 0.16 ps rms random jitter 1 f ref is the frequency of the active reference. 2 f dds is the output frequency of the dds. 3 f loop is the dpll digital loop filter bandwidth. 4 f sysclk is the frequency at the sysclkp and sysclkn pins. 5 f s is the sample rate of the output dac.
ad9548 rev. 0 | page 14 of 112 absolute maximum ratings table 20. parameter rating analog supply voltage (avdd) 2 v digital supply voltage (dvdd) 2 v digital i/o supply voltage (dvdd3) 3.6 v dac supply voltage (avdd3) 3.6 v maximum digital input voltage ?0.5 v to dvdd3 + 0.5 v storage temperature range ?65c to +150c operating temperature range ?40c to +85c lead temperature (soldering 10 sec) 300c junction temperature 150c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution
ad9548 rev. 0 | page 15 of 112 pin configuration and fu nction descriptions 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 dvdd sclk/scl sdio sdo dvdd dvdd3 tclk tms tdo tdi dvdd reset dvdd dvdd nc 17 vss 18 dacoutp 19 dacoutn 20 vss 23 24 25 26 27 28 29 30 31 32 33 34 36 37 35 38 39 40 41 58 57 56 55 54 53 52 51 50 49 48 47 46 45 59 60 61 62 63 64 65 66 78 77 76 75 74 73 72 71 70 69 68 67 79 80 81 82 83 84 85 86 87 88 ad9548 top view (not to scale) 21 avdd3 22 avdd3 42 43 44 nc avdd tdc_vrt tdc_vrb notes 1. nc = no connect. 2. the exposed pad must be connected to ground (vss). refb refbb sysclk_vreg avdd3 avdd avdd sysclkn sysclkp vss vss refa refaa avdd avdd3 m7 m6 m5 m4 dvdd dvdd3 avdd avdd dvdd irq nc avdd3 refdd refcc refc refd m3 m2 m1 m0 avdd3 sysclk_lf nc nc 88-lead lfcsp 12mm 12mm 0.5mm pitch avdd3 dvdd avdd vss clkinn clkinp vss avdd avdd3 avdd avdd out1p out1n avdd3 out2p out3p out3n out2n out_rset avdd3 out0p out0n avdd3 avdd 08022-002 cs/sda figure 2. 88-lead lfcsp pin configuration table 21. pin function descriptions pin no. mnemonic input/ output pin type description 1, 6, 12, 77, 83, 88 dvdd i power 1.8 v digital supply. 2 sclk/scl i 3.3 v cmos serial programming clock. data clock for serial programming. 3 sdio i/o 3.3 v cmos serial data input/output. wh en the device is in 4-wire mode, data is written via this pin. in 3-wire mode, both data reads and writes occur on this pin. there is no internal pull-up/pull-down resistor on this pin. 4 sdo o 3.3 v cmos serial data output. use this pin to read data in 4-wire mode (high impedance in 3-wire mode). there is no internal pull-up/pull-down resistor on this pin. 5 cs /sda i 3.3 v cmos chip select (spi). active low. when programming a device, this pin must be held low. in systems where more than one ad9548 is present, this pin enables individual programming of each ad9548 (in i 2 c? mode, this is a serial data pin). this pin has an internal 10 k pull-up resistor but only in spi mode. 7, 82 dvdd3 i power 3.3 v i/o digital supply. 8 tclk i jtag clock. internal pull-down resistor; no connection if jtag is not used. 9 tms i jtag mode. internal pull-up resistor; no connection if jtag is not used. 10 tdo o jtag output. no connection if jtag is not used 11 tdi i jtag input. internal pull-up resistor; no connection if jtag is not used. 13 reset i 3.3 v cmos chip reset. when this active high pin is asserted, the chip goes into reset. this pin has an internal 50 k pull-down resistor. 14, 15 dvdd i power 1.8 v dac decode digital supply. k eep isolated from the 1.8 v core digital supply. 16, 45, 46 nc no connect. 17, 20, 25, 28, 51, 54 vss o ground analog ground. connect to ground. 18 dacoutp o differential output dac output. dacoutp contains an internal 50 pull-down resistor. 19 dacoutn o differential output complementary dac output. dacoutn contains an internal 50 pull-down resistor. 21, 22 avdd3 i power 3.3 v analog (dac) power supply.
ad9548 rev. 0 | page 16 of 112 pin no. mnemonic input/ output pin type description 23, 24 avdd i power 1.8 v analog (dac) power supply. 26 clkinn i differential input clock distribution input. in standard opera ting mode, this pin is connected to the filtered dacoutn output. this internally bi ased input is typically ac-coupled and, when configured as such, can accept any differential signal whose single-ended swing is at least 400 mv. 27 clkinp i differential input clock distribution input. in standard opera ting mode, this pin is connected to the filtered dacoutp output 29 avdd i power 1.8 v analog (input receiver) power supply. 30 out_rset o current set resistor connect an optional 3.12 k resistor from this pin to ground (see the output current control with an external resistor section). 31, 37, 38, 44 avdd3 i power analog supply for output driver. these pins are normally 3.3 v but can be 1.8 v. pin 31 powers out0x. pin 37 powers out1x. pin 38 powers out2x. pin 44 powers out3x. apply power to these pins even if the corresponding outputs (out0p/ out0n, out1p/ out1n, out2p/ out2n, and out3p/ out3n) are not used. see the power supply partitions section. 32 out0p o lvpecl, lvds, or cmos output 0. this output can be configured as lvpecl, lvds, or single-ended cmos. lvpecl and lvds operation require a 3.3 v output driver power supply. cmos operation can be either 1.8 v or 3.3 v, depending on the output driver power supply. 33 out0n o lvpecl, lvds, or cmos complementary output 0. this output can be configured as lvpecl, lvds, or single-ended cmos. 34, 41 avdd i power 1.8 v analog (output divider) power supply. 35 out1p o lvpecl, lvds, or cmos output 1. this output can be configured as lvpecl, lvds, or single-ended cmos. lvpecl and lvds operation require a 3.3 v output driver power supply. cmos operation can be either 1.8 v or 3.3 v, depending on the output driver power supply. 36 out1n o lvpecl, lvds, or cmos complementary output 1. this output can be configured as lvpecl, lvds, or single-ended cmos. 39 out2p o lvpecl, lvds, or cmos output 2. this output can be configured as lvpecl, lvds, or single-ended cmos. lvpecl and lvds operation require a 3.3 v output driver power supply. cmos operation can be either 1.8 v or 3.3 v, depending on the output driver power supply. 40 out2n o lvpecl, lvds, or cmos complementary output 2. this output can be configured as lvpecl, lvds, or single-ended cmos. 42 out3p o lvpecl, lvds, or cmos output 3. this output can be configured as lvpecl, lvds, or single-ended cmos. lvpecl and lvds operation require a 3.3 v output driver power supply. cmos operation can be either 1.8 v or 3.3 v, depending on the output driver power supply. 43 out3n o lvpecl, lvds, or cmos complementary output 3. this output can be configured as lvpecl, lvds, or single-ended cmos. 47 avdd3 i power 3.3 v analog (system clock) power supply. 48 sysclk_vreg i system clock loop filter voltage regulator. connect a 0.1 f capacitor from this pin to ground. this pin is also the ac ground reference for the integrated sysclk pll multipliers external loop filter (see the sysclk pll multiplier section). 49 sysclk_lf o system clock multiplier loop filter. when using the frequency multiplier to drive the system clock, an external loop filter can be attached to this pin. 50, 55 avdd i power 1.8 v analog (system clock) power supply. 52 sysclkn i differential input complementary system clock input. complementary signal to sysclkp. sysclkn contains internal dc biasing and should be ac-coupled with a 0.01 f capacitor, except when using a crystal, in which case connect the crystal across sysclkp and sysclkn.
ad9548 rev. 0 | page 17 of 112 pin no. mnemonic input/ output pin type description 53 sysclkp i differential input system clock input. sysclkp contains internal dc biasing and should be ac- coupled with a 0.01 f capacitor, except when using a crystal, in which case connect the crystal across sysclkp and sysclkn. single-ended 1.8 v cmos is also an option but can introduce a spur if the duty cycle is not 50%. when using sysclkp as a single-ended input, connect a 0.01 f capacitor from sysclkn to ground. 56, 75 nc i no connection. these pins should be left floating. 59 avdd i power 1.8 v analog power supply. 57, 58 tdc_vrb, tdc_vrt i use capacitive decoupling on these pins (see figure 38 ). 60, 66, 67, 73 avdd3 i power 3.3 v analog (reference input) power supply. 61 refa i differential input reference a input. this internally biased input is typically ac-coupled and, when configured as such, can accept any differential signal with single-ended swing up to 3.3 v. if dc-coupled, input can be lvpecl, cmos, or lvds. 62 refaa i differential input complementary reference a input. comple mentary signal to the input provided on pin 61. the user can configure this pin as a separate single-ended input. 63, 70, 74 avdd i power 1.8 v analog (reference input) power supply. 64 refb i differential input reference b input. this internally biased input is typically ac-coupled and, when configured as such, can accept any differential signal with single-ended swing up to 3.3 v. if dc-coupled, input can be lvpecl, cmos, or lvds. 65 refbb i differential input complementary reference b input. comple mentary signal to the input provided on pin 64. the user can configure this pin as a separate single-ended input. 68 refc i differential input reference c input. this internally biased input is typically ac-coupled and, when configured as such, can accept any differential signal with single-ended swing up to 3.3 v. if dc-coupled, input can be lvpecl, cmos, or lvds. 69 refcc i differential input complementary reference c input. comple mentary signal to the input provided on pin 68. the user can configure this pin as a separate single-ended input. 71 refd i differential input reference d input. this internally biased input is typically ac-coupled and, when configured as such, can accept any differential signal with single-ended swing up to 3.3 v. if dc-coupled, input can be lvpecl, cmos, or lvds. 72 refdd i differential input complementary reference d input. comple mentary signal to the input provided on pin 71. the user can configure this pin as a separate single-ended input. 76 irq o logic interrupt request line. 78, 79, 80, 81, 84, 85, 86, 87 m0, m1, m2, m3, m4, m5, m6, m7 i/o 3.3 v cmos configurable i/o pins. these pins are configured under program control. ep vss o exposed pad the exposed pad must be co nnected to ground (vss).
ad9548 rev. 0 | page 18 of 112 typical performance characteristics f r = input reference clock frequency; f o = clock frequency; f sys = sysclk input frequency; f s = internal system clock frequency; lbw = dpll loop bandwidth; pll off = sysclk pll bypassed; pll on = sysclk pll enabled; i cp = sysclk pll charge pump current; lf = sysclk pll loop filter. avdd, avdd3, and dvdd at nominal supply voltage, f s = 1 ghz, i cp = automatic mode, lf = internal, unless otherwise noted. ?160 ?150 ?140 ?130 ?120 ?110 ?100 ?90 ?80 ? 70 100 1k 10k 100k 1m 10m 100m phase noise (dbc/hz) frequency offset (hz) integrated rms jitter (phase noise): 5khz to 20mhz: 173fs (?75.4dbc) 20khz to 80mhz: 315fs (?70.2dbc) (extrapolated) 08022-068 figure 3. additive phase nois e (output driver = lvpecl), f r = 19.44 mhz, f o = 155.52 mhz, lbw = 1 khz, f sys = 1 ghz, pll off ?160 ?150 ?140 ?130 ?120 ?110 ?100 ?90 ?80 ? 70 100 1k 10k 100k 1m 10m 100m phase noise (dbc/hz) frequency offset (hz) integrated rms jitter (phase noise): 5khz to 20mhz: 333fs (?69.8dbc) 20khz to 80mhz: 430fs (?67.6dbc) (extrapolated) 08022-056 figure 4. additive phase nois e (output driver = lvpecl), f r = 19.44 mhz, f o = 155.52 mhz, lbw = 1 khz, f sys = 50 mhz (crystal), pll on ?160 ?150 ?140 ?130 ?120 ?110 ?100 ?90 ?80 ? 70 100 1k 10k 100k 1m 10m 100m phase noise (dbc/hz) frequency offset (hz) integrated rms jitter (phase noise): 5khz to 20mhz: 103fs (?74.0dbc) 20khz to 80mhz: 160fs (?70.1dbc) 08022-066 figure 5. additive phase nois e (output driver = lvpecl), f r = 19.44 mhz, f o = 311.04 mhz, lbw = 1 khz, f sys = 1 ghz, pll off ?160 ?150 ?140 ?130 ?120 ?110 ?100 ?90 ?80 ? 70 100 1k 10k 100k 1m 10m 100m phase noise (dbc/hz) frequency offset (hz) integrated rms jitter (phase noise): 5khz to 20mhz: 310fs (?64.4dbc) 20khz to 80mhz: 330fs (?63.9dbc) 08022-067 figure 6. additive phase noise (output driver = lvpecl), f r = 19.44 mhz, f o = 311.04 mhz, lbw = 1 khz, f sys = 50 mhz (crystal), pll on
ad9548 rev. 0 | page 19 of 112 ?160 ?150 ?140 ?130 ?120 ?110 ?100 ?90 ?80 ? 70 100 1k 10k 100k 1m 10m 100m phase noise (dbc/hz) frequency offset (hz) integrated rms jitter (phase noise): 5khz to 20mhz: 361fs (?69.0dbc) 20khz to 80mhz: 441fs (?67.3dbc) (extrapolated) 08022-069 figure 7. additive phase noise (output driver = lvpecl), f r = 19.44 mhz, f o = 155.52 mhz, lbw = 1 khz, f sys = 50 mhz, pll on ?160 ?150 ?140 ?130 ?120 ?110 ?100 ?90 ?80 ? 70 10 100 1k 10k 100k 1m 10m 100m phase noise (dbc/hz) frequency offset (hz) integrated rms jitter (phase noise): 5khz to 10mhz: 717fs (?65.1dbc) 12khz to 20mhz: 725fs (?65.0dbc) 20khz to 80mhz: 790fs (?64.3dbc) 08022-044 figure 8. additive phase nois e (output driver = lvpecl), f r = 1 hz, f o = 122.88 mhz, lbw = 0.05 hz, f sys = 20 mhz (ocxo), pll on 100 1k 10k 100k 1m 10m 100m phase noise (dbc/hz) frequency offset (hz) ?160 ?150 ?140 ?130 ?120 ?110 ?100 ?90 ?80 ? 70 integrated rms jitter (phase noise): 5khz to 20mhz: 336fs (?69.7dbc) 20khz to 80mhz: 425fs (?67.6dbc) (extrapolated) 08022-052 figure 9. additive phase nois e (output driver = lvpecl), f r = 8 khz, f o = 155.52 mhz, lbw = 100 hz, f sys = 50 mhz (crystal), pll on ?160 ?150 ?140 ?130 ?120 ?110 ?100 ?90 ?80 ? 70 100 1k 10k 100k 1m 10m 100m phase noise (dbc/hz) frequency (hz) rohde & schwarz sma100 (1ghz) rohde & schwarz sma100 (50mhz) 50mhz crystal 08022-058 figure 10. additive phase noise comparison of sysclk input options (output driver = lvpecl), f r = 19.44 mhz, f o = 311.04 mhz, lbw = 1 khz ?160 ?150 ?140 ?130 ?120 ?110 ?100 ?90 ?80 ? 70 100 1k 10k 100k 1m 10m 100m phase noise (dbc/hz) frequency offset (hz) integrated rms jitter (phase noise): 5khz to 20mhz: 356fs (?69.2dbc) 20khz to 80mhz: 435fs (?67.4dbc) (extrapolated) 08022-054 figure 11. additive phase noise (output driver = lvpecl), f r = 1 hz, f o = 155.52 mhz, lbw = 0.05 hz, f sys = 50 mhz, pll on ?160 ?150 ?140 ?130 ?120 ?110 ?100 ?90 ?80 ? 70 100 1k 10k 100k 1m 10m 100m phase noise (dbc/hz) frequency offset (hz) integrated rms jitter (phase noise): 5khz to 20mhz: 245fs (?72.4dbc) 20khz to 80mhz: 300fs (?64.3dbc) (extrapolated) 08022-051 figure 12. additive phase noise (output driver = lvpecl) , f r = 19.44 mhz, f o = 155.52 mhz, lbw = 1 khz, f sys = 50 mhz (crystal), pll on with 2x frequency multiplier, i cp = 375 a, lf = external (350 khz)
ad9548 rev. 0 | page 20 of 112 rohde & schwarz sma100 (1ghz) rohde & schwarz sma100 (50mhz) 20mhz ocxo ?170 ?160 ?150 ?140 ?130 ?120 ?110 ?100 ? 90 100 1k 10k 100k 1m 10m phase noise (dbc/hz) frequency offset (hz) 08022-053 figure 13. phase noise of sysclk input sources lvds 0 0.2 0.4 0.6 0.8 1.0 0 100 200 300 400 500 600 700 amplitude (v) frequency (mhz) lvpecl 08022-049 figure 14. amplitude vs. toggle rate, lvpecl and lvds 10pf load 20pf load 1.0 1.5 2.0 2.5 3.0 3.5 4.0 0 100 200 300 400 500 amplitude (v) frequency (mhz) 08022-055 figure 15. amplitude vs. toggle rate, 3.3 v cmos (strong mode) ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 10 10 100 1k 10k 100k frequency offset (hz) closed-loop gain (db) 08022-047 closed-loop peaking: 0.04db figure 16. jitter transfer bandwi dth, output driver = lvpecl, f r = 19.44 mhz, f o = 155.52 mhz, lbw = 100 hz (phase margin = 88), f sys = 1 ghz, pll off amplitude (v) frequency (mhz) 08022-062 0.5 1.0 1.5 2.0 0 50 100 150 250 200 5pf load 10pf load 20pf load figure 17. amplitude vs. toggle rate, 1.8 v cmos 10pf load 5pf load 1.0 1.5 2.0 2.5 3.0 3.5 4.0 0 1020304050 amplitude (v) frequency (mhz) 08022-063 figure 18. amplitude vs. toggle rate, 3.3 v cmos (weak mode)
ad9548 rev. 0 | page 21 of 112 lvds lvpecl 50 60 70 80 120 110 100 90 130 140 0 100 200 300 400 500 power (mw) frequency (mhz) 08022-064 figure 19. power consum ption vs. frequency, lvpecl and lvds (single channel) 20 40 60 80 100 120 140 160 0 50 100 150 200 250 300 350 power (mw) frequency (mhz) 10pf load 08022-060 5pf load 20pf load figure 20. power consum ption vs. frequency, 3.3 v cmos (strong mode) ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 012345 differential amplitude (v) time (ns) 08022-050 figure 21. output waveform, lvpecl (400 mhz) power (mw) frequency (mhz) 08022-061 15 20 25 30 35 40 0 50 100 150 200 10pf load 5pf load 20pf load figure 22. power consumption vs. frequency, 1.8 v cmos 20pf load 5pf load 20 22 24 26 28 30 32 34 10 15 20 25 30 35 40 power (mw) frequency (mhz) 10pf load 08022-059 figure 23. power consumption vs. frequency, 3.3 v cmos (weak mode) ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 012345 differenti a l amplitude (v) time (ns) 08022-048 figure 24. output waveform, lvds (400 mhz)
ad9548 rev. 0 | page 22 of 112 ?0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 0 2 4 6 8 10 12 14 16 amplitude (v) time (ns) 20pf load 10pf load 08022-057 figure 25. output waveform, 3.3 v cmos (100 mhz, strong mode) ?0.5 0 0.5 1.0 1.5 2.0 0 2 4 6 8 10 12 14 16 amplitude (v) time (ns) 20pf load 10pf load 08022-065 figure 26. output waveform, 1.8 v cmos (100 mhz) 5pf load 20 pf load ?0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 0 1020304050607080 amplitude (v) time (ns) 08022-046 figure 27. output waveform, 3.3 v cmos (20 mhz, weak mode)
ad9548 rev. 0 | page 23 of 112 input/output termination recommendations ad9548 100? high impedance input downstream device 0.1f 0.1f 3.3v lvds output 08022-003 figure 28. ac-coupled lvds or lvpecl output driver ad9548 100 ? downstream device 3.3v lvpecl- compatible output 08022-004 figure 29. dc-coupled lvds or lvpecl output driver 100? 0.1f 0.1f ad9548 self-biased reference input (optional) 08022-005 figure 30. reference input 100? 0.1f 0.1f ad9548 self-biased sysclk input (optional) 08022-006 figure 31. sysclkx input 0.1f 0.1f ad9548 self-biased clkinx input 08022-007 (optional) 100? figure 32. clkinx input
ad9548 rev. 0 | page 24 of 112 getting started power-on reset the ad9548 monitors the voltage on the power supplies at power-up. when dvdd3 is greater than 2.35 v 0.1 v and dvdd (pin 1, pin 6, pin 12, pin 77, pin 83, and pin 88) is greater than 1.4 v 0.05 v, the device generates a 75 ns reset pulse. the power-up reset pulse is internal and independent of the reset pin. this internal power-up reset sequence eliminates the need for the user to provide external power supply sequencing. within 45 ns after the leading edge of the internal reset pulse, the m0 to m7 multifunction pins behave as high impedance digital inputs and remain so until programmed otherwise. initial pin programming during a device reset (either via the power-up reset pulse or the reset pin), the multifunction pins (m0 to m7) behave as high impedance inputs, but upon removal of the reset condition, level-sensitive latches capture the logic pattern present on the multifunction pins. the ad9548 requires that the user supply the desired logic state to the m0 to m7 pins by means of pull-up and/or pull-down resistors (nominally 10 k to 30 k). the initial state of the m0 to m7 pins following a reset is referred to as fncinit, bits[7:0]. bits[7:0] of fncinit map directly to the logic states of m7:0, respectively. the three lsbs of fncinit (fncinit, bits[2:0]) determine whether the serial port interface behaves according to the spi or i 2 c protocol. specifically, fncinit, bits[2:0] = 000 selects the spi interface, while any other value selects the i 2 c port with the three lsbs of the i 2 c bus address set to the value of fncinit, bits[2:0]. the five msbs of fncinit (fncinit, bits[7:3]) determine the operation of the eeprom loader. on the falling edge of reset, if fncinit, bits[7:3] = 00000, then the eeprom contents are not transferred to the control registers and the device registers assume their default values. however, if fncinit, bits[7:3] 00000, then the eeprom controller transfers the contents of the eeprom to the control registers with condition = fncinit, bits[7:3] (see the eeprom section). device register programming the initial state of the m0 to m7 pins establishes the serial i/o port protocol (spi or i 2 c). using the appropriate serial port protocol, and assuming that an eeprom download is not used, program the device according to the recommended sequence described in the program the system clock functionality section through the generate the output clock section. program the system clock functionality t he system clock parameters reside in the 0100 register address space. they include the following: ? system clock pll controls ? system clock period ? system clock stability timer it is essential to program the system clock period because many of the ad9548 subsystems rely on this value. it is highly recommended to program the system clock stability timer, as well. this is especially important when using the system clock pll but also applies if using an external system clock source, especially if the external source is not expected to be completely stable when power is applied to the ad9548. initialize the system clock after the system clock functionality is programmed, issue an i/o update using register 0005, bit 0 to invoke the system clock settings. calibrate the system clock (o nly if using sysclk pll) set the calibrate system clock bit in the sync/cal register (address 0a02, bit 0) and issue an i/o update. then clear the calibrate system clock bit and issue another i/o update. this action allows time for the calibration to proceed while pro- gramming the remaining device registers. program the multifunction pins (optional) this step is required only if the user intends to use any of the multifunction pins for status or control. the multifunction pin parameters resides in the 0200 to 0207 register address space. the default configuration of the multifunction pins is as an undesignated high impedance input pin. program the irq functionality (optional) t his step is required only if the user intends to use the irq feature. irq control resides in the 0200 to 0207 register address space. it includes the following: ? irq pin mode control ? irq mask the irq mask default values prevent interrupts from being generated. the irq pin mode default is open-drain nmos. program the watchdog timer (optional) this step is required only if the user intends to use it. watchdog timer control resides in the 0200 register address space. the watchdog timer is disabled by default. program the dac full-scal e current (optional) this step is required only if the user intends to use a full-scale current setting other than the default value. dac full-scale current control resides in the 0200 register address space. program the digital phas e-locked loop (dpll) t he dpll parameters reside in the 0300 register address space. they include the following: ? free-run frequency (dds frequency tuning word) ? dds phase offset ? dpll pull-in range limits ? dpll closed-loop phase offset ? phase slew control (for hitless reference switching)
ad9548 rev. 0 | page 25 of 112 ? tuning word history control (for holdover operation) program the clock distribution outputs t he clock distribution parameters reside in the 0400 register address space. they include the following: ? output power-down control ? output enable (disabled by default) ? output synchronization ? output mode control ? output divider functionality program the reference inputs t he reference input parameters reside in the 0500 register address space. they include the following: ? reference power-down ? reference logic family ? reference profile assignment control ? phase build-out control program the reference profiles t he reference profile parameters reside in the 0600 to 0700 register address space. they include the following: ? reference priority ? reference period ? reference period tolerance ? reference validation timer ? reference redetect timer ? digital loop-filter coefficients ? reference prescaler (r-divider) ? feedback dividers (s, u, and v) ? phase and frequency lock detector controls generate the reference acquisition after the registers are programmed, issue an i/o update using register 0005, bit 0 to invoke all of the register settings programmed up to this point. if the settings are programmed for manual profile assignment, the dpll locks to the first available reference that has the highest priority. if the settings are programmed for automatic profile assignment, then write to the reference profile detect register (address 0a0d) to select the state machines that require starting. next, issue an i/o update (address 0005, bit 0) to start the selected state machines. upon completion of the reference detection sequence, the dpll locks to the first available reference with the highest priority. generate the output clock if the registers are programmed for automatic clock distribution synchronization via dpll phase or frequency lock, the syn- thesized output signal appears at the clock distribution outputs (assuming the output is enabled and that the dds output signal has been routed to the clkin input pins). otherwise, set and then clear the sync distribution bit (address 0a02, bit 1) or use a multifunction pin input (if programmed accordingly) to generate a clock distribution sync pulse, which causes the synthesized output signal to appear at the clock distribution outputs.
ad9548 rev. 0 | page 26 of 112 theory of operation tw clamp and history prog. digital loop filter tdc/pfd r s digital pll core holdover logic control logic low noise clock multiplier amp sysclk port input ref monitor irq and status logic digital interface irq sysclkn sysclkp clkinn clkinp m0 to m7 refa refaa out0p phase controller dds/dac ad9548 4 or 8 out0n out_rset out1p out1n out2p out2n out3p out3n post div post div post div post div clock distribution refb refbb refc refcc refd refdd differential or single-ended external analog filter 08022-009 figure 33. detailed block diagram overview the ad9548 provides clocking outputs directly related in phase and frequency to the selected (active) reference but with jitter characteristics primarily governed by the system clock. the ad9548 supports up to eight reference inputs and a wide range of reference frequencies. the core of this product is a digital phase-locked loop (dpll). the dpll has a programmable digital loop filter that greatly reduces jitter transferred from the active reference to the output. the ad9548 supports both manual and automatic holdover. while in holdover, the ad9548 continues to provide an output as long as the dac sample clock is present. the holdover output frequency is a time average of the output frequency history just prior to the transition to the holdover condition. the device offers manual and automatic reference switchover capability if the active reference is degraded or fails completely. a direct digital synthesizer (dds) and integrated dac consti- tute a digitally controlled oscillator (dco). the dco output is a sinusoidal signal (450 mhz maximum) at a frequency deter- mined by the active reference frequency and the programmed values of the reference prescaler (r) and feedback divider (s). although not explicitly shown in figure 33 , the s-divider has both an integer and fractional component, which is similar to a fractional-n synthesizer. the sysclkx input provides the sample clock for the dac, which is either a directly applied high frequency source or a low frequency source coupled with the integrated pll-based frequency multiplier. the low frequency option also allows for the use of a crystal resonator connected directly across the sysclkx inputs. the dac output routes directly off-chip, where an external filter removes the sampling artifacts before returning the signal on-chip at the clkinx inputs. once on-chip, an integrated comparator converts the filtered sinusoidal signal to a clock signal (square wave) with very fast rise and fall times. the clock distribution section provides four output drivers. each driver is programmable either as a single differential lvpecl/lvds output or as a dual single-ended cmos output. furthermore, each of the four outputs has a dedicated 30-bit programmable postdivider. the clock distribution section operates at up to 725 mhz. this enables use of a band-pass reconstruction filter (for example, a saw filter) to extract a nyquist image from the dac output spectrum, thereby allowing output frequencies that exceed the typical 450 mhz limit at the dac output.
ad9548 rev. 0 | page 27 of 112 reference clock inputs four pairs of pins provide access to the reference clock receivers. each pair is configurable either as a single differential receiver or as two independent single-ended receivers. to accommodate input signals with slow rising and falling edges, both the differential and single-ended input receivers employ hysteresis. hysteresis also ensures that a disconnected or floating input does not cause the receiver to oscillate spontaneously. when configured for differential operation, the input receivers accommodate either ac- or dc-coupled input signals. the receiver is internally dc biased in order to handle ac-coupled operation. when configured for single-ended operation, the input receivers exhibit a pull-down load of 45 k (typical). three user-programmable threshold voltage ranges are available for each single-ended receiver. reference monitors the reference monitors depend on a known and accurate system clock period. therefore, the functioning of the reference monitors is not reliable until the system clock is stable. to avoid an incorrect valid indication, the reference monitors indicate fault status until the system clock stability timer expires (see the system clock stability timer section). reference period monitor each reference input has a dedicated monitor that repeatedly measures the reference period. the ad9548 uses the reference period measurements to determine the validity of the reference based on a set of user provided parameters in the profile register area of the register map (see the profile registers (register 0600 to register 07ff) section). the ad9548 also uses the reference period monitor to assign a particular reference to a profile when the user programs the device for automatic profile assignment. the monitor works by comparing the measured period of a particular reference input with the parameters stored in the profile register assigned to that same reference input. the parameters include the reference period, an inner tolerance, and an outer tolerance. a 50-bit number defines the reference period in units of femtoseconds. the 50-bit range allows for a reference period entry of up to 1.125 sec. however, an actual reference signal with a period in excess of 1 sec is beyond the recommended operating range of the device. a 20-bit number defines the inner and outer tolerances. the value stored in the register is the reciprocal of the tolerance specification. for example, a tolerance specification of 50 ppm yields a register value of 1/(50 ppm) = 1/0.000050 = 20,000 (0x04e20). the use of two tolerance values provides hysteresis for the monitor decision logic. the inner tolerance applies to a previously faulted reference and specifies the largest period tolerance that a previously faulted reference can exhibit before it qualifies as nonfaulted. the outer tolerance applies to an already nonfaulted reference. it specifies the largest period tolerance that a nonfaulted reference can exhibit before being faulted. to produce decision hysteresis, the inner tolerance must be less than the outer tolerance. that is, a faulted reference must meet tighter requirements to become nonfaulted than a nonfaulted reference must meet to become faulted. reference validation timer each reference input has a dedicated validation timer. the validation timer establishes the amount of time that a previously faulted reference must remain fault free before the ad9548 declares it nonfaulted. the timeout period of the validation timer is programmable via a 16-bit register (see the validation register contained within each of the eight profile registers in the register map, address 0600 to address 07ff). the 16-bit number stored in the validation register represents units of milliseconds, which yields a maximum timeout period of 65,535 ms. note that a validation period of 0 must be programmed to disable the validation timer. with the validation timer disabled, the user must validate a reference manually via the force validation timeout register (address 0a0e). reference redetect timer each reference input has a dedicated redetect timer. the redetect timer is useful only with the device programmed for automatic profile selection. the redetect timer establishes the amount of time that a reference must remain faulted before the ad9548 attempts to reassign it to a new profile. the timeout period of the redetect timer is programmable via a 16-bit register (see the redetect timeout register contained within each of the eight profile registers in the register map, address 0600 to address 07ff). the 16-bit number stored in the redetect timeout register represents units of milliseconds, which yields a maximum timeout period of 65,535 ms. note that a timeout period of 0 must be programmed to disable the redetect timer. reference validation override control register 0a0e to register 0a10 provide the user with the ability to override the reference validation logic enabling a certain level of troubleshooting capability. each of the eight input references has a dedicated block of validation logic as shown in figure 34 . the state of the valid signal at the output is what defines a particular reference as valid (1) or not (0), which includes the validation period (if activated) as prescribed by the validation timer. the override controls are the three control bits on the left side of the diagram.
ad9548 rev. 0 | page 28 of 112 dq r 0 1 en faulted valid force validation timeout ref fault ref monitor bypass ref monitor override register control bits reference validation logic (8 copies, 1 per reference input) reference monitor r validation timer timeout 08022-010 figure 34. reference validation override the main feature to note is that any time faulted = 1, the output latch is reset, which forces valid = 0 (indicating an invalid refer- ence) regardless of the state of any other signal. under the default condition (that is, all three control bits are 0), the reference monitor is the primary source of the validation process. this is because, under the default condition, the ref fault signal from the reference monitor is identically equal to the faulted signal. t he function of the faulted signal is fourfold. ? any time faulted = 1, then valid = 0, regardless of the state of any other control signal. therefore, faulted = 1 indicates an invalid reference. ? any time the faulted signal transitions from 0 to 1 (that is, from nonfaulted to faulted), the validation timer is momentarily reset, which means that, once it is enabled, it must exhaust its full counting sequence before it expires. ? when faulted = 0 (that is, the reference is not faulted), the validation timer is allowed to perform its timing sequence. when faulted = 1 (that is, the reference is faulted), the validation timer is reset and halted. ? the faulted signal passes through an inverter, converting it to a nonfaulted signal, which appears at the input of the valid latch. this allows the valid latch to capture the state of the nonfaulted signal when the validation timer expires. the ref monitor bypass control bit enables bypassing of the ref fault signal generated by the reference monitor. when ref monitor bypass = 1, the state of the faulted signal is dictated by the ref monitor override control bit. this is useful when the user relies on an external reference monitor rather than the internal monitor resident in the device. the user programs the ref monitor override bit based on the status of the external monitor. on the other hand, when ref monitor bypass = 0, the ref monitor override control bit allows the user to manually test the operation of both the valid latch and the validation timer. in this case, the user relies on the signal generated by the internal reference monitor (ref fault) but uses the ref monitor override bit to emulate a faulted reference. that is, when ref monitor override = 1, then faulted = 1, but when ref monitor override = 0, then faulted = ref fault. in addition, the user has the ability to emulate a timeout of the validation timer via the appropriate force validation timeout control bit in register 0a0e. writing a logic 1 to any of these autoclearing bits triggers the valid latch, which is identically equivalent to a timeout of the validation timer. reference profiles t he ad9548 has eight independent profile registers. a profile register contains 50 bytes that establish a particular set of device parameters. each of the eight input references can be assigned to any one of the eight profiles (that is, more than one reference can be assigned to the same profile). the profiles allow the user to prescribe the specific device functionality that should take effect when one of the input references (assigned to the profile) becomes the active reference. each profile register has the same format and stores the following device parameters: ? reference priority ? reference period value (in femtoseconds) ? inner tolerance value (1/tolerance) ? outer tolerance value (1/tolerance) ? validation timer value (milliseconds) ? redetect timer value (milliseconds) ? digital loop filter coefficients ? reference prescaler setting (r-divider) ? feedback divider settings (s, u, and v) ? dpll phase lock detector threshold level ? dpll phase lock detector fill rate ? dpll phase lock detector drain rate ? dpll frequency lock detector threshold level ? dpll frequency lock detector fill rate ? dpll frequency lock detector drain rate reference-to-profile assignment control the user can manually assign a reference to a profile or let the device make the assignment automatically. the manual reference profile selection register (address 0503 to address 0506) is where the user programs whether a reference-to-profile assignment is manual or automatic. the manual reference profile selection register is a 4-byte register partitioned into eight half bytes (or nibbles). the eight nibbles form a one-to- one correspondence with the eight reference inputs: one nibble for ref a, the next for ref aa, and so on. for a reference configured as a differential input, however, the device ignores the nibble associated with the two-letter input. for example, if
ad9548 rev. 0 | page 29 of 112 the b reference is differential, then only the refb nibble matters (the device ignores the refbb nibble). the msb of each nibble is the manual profile bit, whereas the three lsbs of each nibble identify one of the eight profiles (0 to 7). a logic 1 for the manual profile bit assigns the associated reference to the profile identified by the three lsbs of the nibble. a logic 0 for the manual profile bit configures the associated reference for automatic reference-to-profile assignment (the three lsbs are ignored in this case). note that references configured for automatic reference-to-profile assignment require activation (see the reference-to-profile assignment state machine section). reference-to-profile assignment state machine the functional flexibility of the ad9548 resides in the way that it assigns a particular input reference to one of the eight reference profiles. the reference-to-profile assignment state machine effectively builds a reference-to-profile table that maps the index of each input reference to a profile (see table 22 ). each entry in the profile column consists of a profile number (0 to 7) or a null value. a null value appears when a reference- to-profile assignment does not exist for a particular reference input (following a reset, for example). the information in table 22 appears in the register map (register 0d0c to register 0d13) so that the user has access to the reference-to-profile assignments on a real-time basis. register 0d0c contains the information for ref a, register 0d0d contains the inform- ation for ref aa, and so on to register 0d13 for ref dd. bit 7 of each register is the null indicator for that particular reference. if bit 7 = 0, then the profile assignment for that particular reference is null. if bit 7 = 1, then that particular reference is assigned to the profile (0 to 7) identified by bits[6:4]. note that bits[6:4] are meaningless unless bit 7 = 1. table 22. reference-to-profile table reference input reference index profile a 0 profile number (or null value) aa 1 profile number (or null value) b 2 profile number (or null value) bb 3 profile number (or null value) c 4 profile number (or null value) cc 5 profile number (or null value) d 6 profile number (or null value) dd 7 profile number (or null value) following a reset, the reference-to-profile assignment state machine is inactive to avoid improperly assigning a reference to a profile before the system clock stabilizes. the reason is that the state machine relies on accurate information from the reference monitors, which, in turn, rely on a stable system clock. because the reference-to-profile assignment state machine is inactive at power-up, the user must initiate it manually by writing to the reference profile detect register (address 0a0d). the state machine activates immediately, unless the system clock is not stabilized, in which case, activation occurs upon expiration of the system clock stability timer. note that initialization of the state machine is on a per-reference basis. that is, each reference input is associated with an independent initialization control bit. once initialized for processing a reference, the state machine continuously monitors that reference until the occurrence of a device reset. this is true even when the user programs a reference for manual profile selection, in which case, the state machine associated with that particular reference operates with its activity masked. the masked background activity allows for seamless operation if the user subsequently reprograms the reference for automatic profile selection. reference-to-profile assignment when a reference is programmed for manual profile assignment (see register 0503 to register 0506), the reference-to-profile assignment state machine simply puts the programmed manual profile number into the profile column of the reference-to- profile table (see table 22 ) in the row associated with the appro- priate reference. however, when the user programs a reference for automatic profile assignment, the state machine must figure out which profile to assign to the reference. as long as a null entry appears in the reference-to-profile table for a particular input reference, the validation logic for that reference enters a period estimation mode. note that a null entry is the default state following a reset, but it also occurs when a reference redetect timer expires. the period estimation mode enables the validation logic to make a blind estimate of the period of the input reference with a tolerance of 0.1%. the validation logic remains in the period estimation mode until it successfully estimates the reference period. upon a successful reference period measurement by the validation logic, the state machine compares the measured period to the nominal reference period programmed into each of the eight profiles. the state machine assigns the reference to the profile with the closest match to the measured period. if more than one profile exactly matches the reference period, then the state machine chooses the profile with the lowest numeric index. for example, if the reference period in both profile 3 and profile 5 matches the measured period, then profile 3 is given the assignment. to safeguard against making a poor reference-to-profile assignment, the state machine ensures that the measured reference period is within 6.25% of the nominal reference period that appears in the closest match profile. otherwise, the state machine does not make a profile assignment and leaves the null entry in the reference-to-profile table. as long as there are input references programmed for automatic profile assignment, and for which the profile assignment is null, the state machine continues to cycle through those references searching for a profile match. furthermore, unless an input
ad9548 rev. 0 | page 30 of 112 reference is assigned to a profile, it is considered invalid and excluded as a candidate for a reference switchover. reference switchover an attractive feature of the ad9548 is its versatile reference switchover capability. the flexibility of the reference switchover functionality resides in a sophisticated prioritization algorithm coupled with register-based controls. this scheme provides the user with maximum control over the state machine that handles reference switchover. t he main reference switchover control resides in the loop mode register (address 0a01). the user selection mode bits (register 0a01, bits[4:3]) allow the user to select one of the reference switchover state machines four operating modes, as follows: ? automatic mode (address a01, bits[4:3] = 00) ? fallback mode (address 0a01, bits[4:3] = 01) ? holdover mode (address 0a01, bits[4:3] = 10) ? manual mode (address 0a01, bits[4:3] = 11) in automatic mode, a fully automatic priority-based algorithm selects which reference is the active reference. when programmed for automatic mode, the device ignores the user selection reference bits (register 0a01, bits[2:0]). however, when pro- grammed for any of the other three modes, the device makes use of the user reference bits. these bits specify a particular input reference (000 = ref a, 001 = ref aa ..., 111 = ref dd). in fallback mode, the user reference is the active reference whenever it is valid. otherwise, the device switches to a new reference using the automatic, priority-based algorithm. in holdover mode, the user reference is the active reference whenever it is valid. otherwise, the device switches to holdover mode. in manual mode, the user reference is the active reference whether it is valid or not. note that, when using this mode, the user must program the reference-to-profile assignment (see register 0503 to register 0506) as manual for the particular reference declared as the user reference. the reason is that if the user reference fails and its redetect timer expires, then its profile assignment (shown in tabl e 22 ) becomes null. this means that the active reference (user reference) does not have an assigned profile, which places the ad9548 into an undefined state. the user also has the option to force the device directly into holdover or free-run operation via the user holdover and user free-run bits (register 0a01, bit 6 and bit 5, respectively]). in free-run mode, the free running frequency tuning word register (address 0300 to address 0305) defines the dds output frequency. in holdover mode, the dds output frequency depends on the holdover control settings (see the holdover section). automatic priority-based reference switchover the ad9548 has a two-tiered, automatic, priority-based algorithm that is in effect for both automatic and fallback reference switchover. the algorithm relies on the fact that each reference profile contains both a selection priority and a promoted priority. the selection and promoted priority values range from 0 (highest priority) to 7 (lowest priority). the selection priority determines the order in which references are chosen as the active reference. the promoted priority is a separate priority value given to a reference only after it becomes the active reference. an automatic reference switchover occurs on failure of the active reference or when a previously failed reference becomes valid and its selection priority is higher than the promoted priority of the currently active reference (assuming that the automatic or fallback reference switchover is in effect). when performing an automatic reference switchover, the ad9548 chooses a reference based on the priority settings within the profiles. that is, the device switches to the reference with the highest selection priority (lowest numeric priority value). it does so by using the reference-to-profile table (see table 22 ) to determine the reference associated with the profile exhibiting the highest priority. if multiple references share the same profile, then the device chooses the reference having the lowest index value. for example, if the a, b, and cc references (index 0, index 2, and index 5, respectively) share the same profile, then a switchover to reference a occurs because reference a has the lowest index value. note, however, that only valid references are included in switchover of the selection process. the switchover control logic ignores any reference with a status indication of invalid. the promoted priority parameter allows the user to assign a higher priority to a reference after it becomes the active reference. for example, suppose four references have a selection priority of 3 and a promoted priority of 1, and the remaining references have a selection priority or 2 and a promoted priority of 2. now, assume that one of the priority 3 references becomes active because all of the priority 2 references have failed. some- time later, however, a priority 2 reference becomes valid. the switchover logic normally attempts to automatically switch over to the priority 2 reference because it has higher priority than the presently active priority 3 reference. however, because the priority 3 reference is active, its promoted priority of 1 is in effect. this is a higher priority than the newly validated references priority of 2, so the switchover does not occur. this mechanism enables the user to give references preferential treatment while they are selected as the active reference. an example of promoted vs. nonpromoted priority switching appears in state diagram form in figure 35 . figure 36 shows a block diagram of the interrelationship between the reference inputs, monitors, validation logic, profile selection, and priority selection functionality.
ad9548 rev. 0 | page 31 of 112 a active b active c active a faulted b faulted all valid initial state a valid b valid a valid b valid input priority promoted a0 0 b1 0 c2 1 d3 2 priority table common without promotion with promotion 08022-011 figure 35. example of priority promotion profile selection validation logic priority selection r monitors a/aa b/bb c/cc d/dd tdc loop controller ?? ? ??? 08022-012 figure 36. reference clock block diagram phase build-out reference switching phase build-out reference switching is the term given to a reference switchover that completely masks any phase difference between the previous reference and the new reference. that is, there is virtually no phase change detectable at the output when a phase build-out switchover occurs. the ad9548 handles phase build-out switching based on whether the new reference is a phase master. a phase master is any reference with a selection priority value that is less than the phase master threshold priority value (that is, higher priority). the phase master threshold priority value resides in the phase build-out switching register (address 0507), whereas the selection priority resides in the profile registers (address 0600 to address 07ff). by default, the phase master threshold priority is 0; therefore, no references can be phase masters until the user changes the phase master threshold priority. whenever the ad9548 switches from one reference to another, it compares the selection priority value stored in the profile assigned to the new reference with the phase master threshold priority. the ad9548 performs a phase build-out switchover only if the new reference is not a phase master. hitless reference switchin g (phase slew control) hitless reference switching is the term given to a reference switchover that limits the rate of change of the phase of the output clock while the pll is in the process of acquiring phase lock. this prevents the output frequency offset from becoming excessive. the all-digital nature of the dpll core (see the digital pll (dpll) core section) gives the user numerical control of the rate at which phase changes occur at the dpll output. when enabled, a phase slew controller monitors the phase difference between the feedback and reference inputs to the dpll. the phase slew controller has the ability to place a user-specified limit on the rate of change of phase, thus providing a mechanism for hitless reference switching. the user sets a limit on the rate of change of phase by storing the appropriate value in the 16-bit phase slew rate limit register (address 0316 to address 0317). the 16-bit word (representing ns/sec) puts an upper bound on the rate of change of the phase at the output of the dpll during a reference switchover. a phase slew rate value of 0 (default) disables the phase slew controller. the accuracy of the phase slew controller depends on both the phase slew limit value and the system clock frequency. generally, an increase in the phase slew rate limit value or a decrease in the system clock frequency tends to reduce the error. as such, the accuracy is best for the largest phase slew limit value and the lowest system clock frequency. for example, assuming the use of a 1 ghz system clock, a phase slew limit value of 315 ns/sec (or more) ensures an error of less than 10%, whereas a phase slew rate limit value above ~3100 ns/sec ensures an error of less than 1%. on the other hand, assuming the use of a 500 mhz system clock, the same phase slew rate limit values ensure an error of less than 5% or 0.5%, respectively.
ad9548 rev. 0 | page 32 of 112 digital pll (dpll) core dpll overview a diagram of the digital pll core of the ad9584 appears in figure 37 . the phase/frequency detector, feedback path, lock detectors, phase offset, and phase slew rate limiting that comprise this second generation dpll are all digital implementations. r + 1 ref a tdc and pfd digital loop filter dds/ dac dacout closed-loop phase offset phase slew limit lock detect ref dd dppl core 2 f r f tdc f dds s + 1 + u/v 08022-013 figure 37. digital pll core the start of the dpll signal chain is the reference signal, f r , which is the frequency of the reference input. a reference prescaler reduces the frequency of this signal by an integer factor, r + 1, where r is the 30-bit value stored in the appropriate profile register and 0 r 1,073,741,823. therefore, the freq- uency at the output of the r-divider (or the input to tdc) is 1 + = r f f r tdc a time-to-digital converter (tdc) samples the output of the r-divider. the tdc/pfd produces a time series of digital words and delivers them to the digital loop filter. the digital loop filter offers the following advantages: ? determination of the filter response by numeric coefficients rather than by discrete component values ? the absence of analog components (r/l/c), which eliminates tolerance variations due to aging ? the absence of thermal noise associated with analog components ? the absence of control node leakage current associated with analog components (a source of reference feed- through spurs in the output spectrum of a traditional analog pll) the digital loop filter produces a time series of digital words at its output and delivers them to the frequency tuning input of a dds, with the dds replacing the function of the vco in an analog pll. the digital words from the loop filter tend to steer the dds frequency toward frequency and phase lock with the input signal (f tdc ). the dds provides an analog output signal via an integrated dac, effectively mimicking the operation of an analog vco. the dpll includes a feedback divider that causes the dds to operate at an integer-plus-fractional multiple (s + 1 + u/v) of f tdc . s is the 30-bit value stored in the profile register and has a range of 7 s 1,073,741,823. u and v are the 10-bit numer- ator and denominator values of the optional fractional divide component and are also stored in the profile register. together they establish the nominal dds frequency (f dds ), given by ? ? ? ? ? ? ++ + = v u s r f f r dds 1 1 normally, fractional-n designs exhibit distinctive phase noise and spurious artifacts resulting from the modulation of the integer divider based on the fractional value. such is not the case for the ad9548 because it uses a purely digital means to determine phase errors. because the phase errors incurred by modulating the feedback divider are deterministic, it is possible to compensate for them digitally. the result is a fractional-n pll with no discernable modulation artifacts. tdc/pfd the tdc is a highly integrated functional block that incor- porates both analog and digital circuitry. there are two pins associated with the tdc that the user must connect to external components. figure 38 shows the recommended component values and their connections. for best performance, place components as close as possible to the device pins. components with low effective series resistance (esr) and low parasitic inductance yield the best results. ad9548 10f 0.1f 0.1f 0.1f tdc_vrt tdc_vrb 58 57 08022-014 figure 38. tdc pin connections the phase-frequency detector (pfd) is an all-digital block. it compares the digital output from the tdc (which relates to the active reference edge) with the digital word from the feedback block (which relates to the rollover edge of the dds accumulator after division by the feedback divider). it uses a digital code pump and digital integrator (rather than a conventional charge pump and capacitor) to generate the error signal that steers the dds frequency toward phase lock. closed-loop phase offset the all-digital nature of the tdc/pfd provides for numerical control of the phase offset between the reference and feedback edges. this allows the user to adjust the relative timing of the distribution output edges relative to the reference input edges by programming the 40-bit fixed phase lock offset register
ad9548 rev. 0 | page 33 of 112 (address 030f to address 0313). the 40-bit word is a signed (twos complement) number that represents units of picoseconds. in addition, the user can adjust the closed-loop phase offset (positive or negative) in incremental fashion. to do so, program the desired step size in the 16-bit incremental phase lock offset step size register (address 0314 to address 0315). this is an unsigned number that represents units of picoseconds. the programmed step size is added to the current closed-loop phase offset each time the user writes a logic 1 to the increment phase offset bit (register 0a0c, bit 0). conversely, the programmed step size is subtracted from the current closed-loop phase offset each time the user writes a logic 1 to the decrement phase offset bit (register 0a0c, bit 1). the serial i/o port control logic clears both of these bits automatically. the user can remove the incre- mentally accumulated phase by writing a logic 1 to the reset incremental phase offset bit (register 0a0c, bit 2), which is also cleared automatically. alternatively, rather than using the serial i/o port, the multifunction pins can be set up to perform the increment, decrement, and clear functions. note that the incremental phase offset is completely indepen- dent of the offset programmed into the fixed phase lock offset register. however, if the phase slew limiter is active (see the hitless reference switching (phase slew control) section), then any instantaneous change in closed-loop phase offset (fixed or incremental) will be subject to possible slew limitation by the action of the phase slew limiter. programmable digital loop filter the ad9548 loop filter is a third order digital iir filter that is analogous to the third order analog loop shown in figure 39 . c 3 c 2 c 1 r 2 r 3 08022-015 figure 39. third order analog loop filter the filter requires four coefficients as shown in figure 40 . the ad9548 evaluation board software automatically generates the required loop filter coefficient values based on the users design criteria. the calculating digital filter coefficients section contains the design equations for calculating the loop filter coefficients manually. loop filter (third order iir) in out fractional (16-bit) 1/2 x (6-bit) 2 x (3-bit) 2 x (4-bit) fractional (17-bit) 1/2 x (6-bit) fractional (17-bit) 1/2 x (6-bit) fractional (15-bit) 1/2 x (5-bit) 48 51 08022-016 figure 40. third order digital iir loop filter each coefficient has a fractional component representing a value from 0 up to, but not including, unity. each coefficient also has an exponential component representing a power of 2 with a negative exponent. that is, the user enters a positive number (x) that the hardware interprets as a negative exponent of two (2 ?x ). thus, the , , and coefficients always represent values less than unity. the coefficient, however, has two additional exponential components, but the hardware interprets these as a positive exponent of 2 (that is, 2 x ). this allows the coefficient to be a value greater than unity. the positive exponent appears as two separate terms in order to provide sufficient dynamic range. dpll phase lock detector the dpll contains an all-digital phase lock detector. the user controls the threshold sensitivity and hysteresis of the phase detector via the profile registers. the phase lock detector behaves in a manner analogous to water in a tub (see figure 41 ). the total capacity of the tub is 4096 units with ?2048 denoting empty, 0 denoting the 50% point, and +2048 denoting full. the tub also has a safeguard to prevent overflow. furthermore, the tub has a low water mark at ?1024 and a high water mark at +1024. to change the water level, the user adds water with a fill bucket or removes water with a drain bucket. the user specifies the size of the fill and drain buckets via the 8-bit fill rate and drain rate values in the profile registers. the water level in the tub is what the lock detector uses to determine the lock and unlock conditions. whenever the water level is below the low water mark (?1024), the detector indicates an unlock condition. conversely, whenever the water level is above the high water mark (+1024), the detector indicates a lock condition. while the water level is between the marks, the detector simply holds its last condition. this concept appears graphically in figure 41 , with an overlay of an example of the instantaneous water level (vertical) vs. time (horizontal) and the resulting lock/unlock states. during any given pfd phase error sample, the detector either adds water with the fill bucket or removes water with the drain bucket (one or the other but not both). the decision of whether to add or remove water depends on the threshold level specified by the user. the phase lock threshold value is a 16-bit number stored in the profile registers and is expressed in picoseconds. thus, the phase lock threshold extends from 0 ns to 65.535 ns and represents the magnitude of the phase error at the output of the pfd. the phase lock detector compares each phase error sample at the output of the pfd to the programmed phase threshold value. if the absolute value of the phase error sample is less than or equal to the programmed phase threshold value, then the detector control logic dumps one fill bucket into the tub. otherwise, it removes one drain bucket from the tub. notice that it is not the polarity of the phase error sample, but its magnitude relative to the phase threshold value, that determines whether to fill or drain. if more filling is taking place than
ad9548 rev. 0 | page 34 of 112 direct digital synthesizer draining, the water level in the tub eventually rises above the high water mark (+1024), which causes the phase lock detector to indicate lock. if more draining is taking place than filling, then the water level in the tub eventually falls below the low water mark (?1024), which causes the phase lock detector to indicate unlock. the ability to specify the threshold level, fill rate, and drain rate enables the user to tailor the operation of the phase lock detector to the statistics of the timing jitter associated with the input reference signal. dds overview one of the primary building blocks of the digital pll is a direct digital synthesizer (dds). the dds behaves like a sinusoidal signal generator. the frequency of the sinusoid generated by the dds is determined by a frequency tuning word (ftw), which is a digital (that is, numeric) value. unlike an analog sinusoidal generator, a dds uses digital building blocks and operates as a sampled system. thus, it requires a sampling clock (f s ) that serves as the fundamental timing source of the dds. the accumulator behaves as a modulo-2 48 counter with a programmable step size (ftw). a block diagram of the dds appears in figure 42 . 0 2048 ?2048 1024 ?1024 lock level unlock level locked unlocked previous state fill rate drain rate 08022-017 the input to the dds is the 48-bit ftw. the ftw serves as a step size value. on each cycle of f s , the accumulator adds the value of the ftw to the running total at its output. for example, given ftw = 5, the accumulator counts by fives, incrementing on each f s cycle. over time, the accumulator reaches the upper end of its capacity (2 48 in this case), at which point, it rolls over but retains the excess. the average rate at which the accumulator rolls over establishes the frequency of the output sinusoid. the average rollover rate of the accumulator establishes the output frequency (f dds ) of the dds and is given by figure 41. lock detector diagram note that whenever the ad9548 enters the free-run or holdover mode, the dpll phase lock detector indicates unlocked. in addition, whenever the ad9548 performs a reference switch- over, the state of the lock detector prior to the switch is preserved during the transition period. dpll frequency lo ck detector s dds f ftw f ? ? ? ? ? ? = 48 2 the operation of the frequency lock detector is identical to that of the phase lock detector. the only difference is that the fill or drain decision is based on the period deviation between the reference and feedback signals of the dpll instead of the phase error at the output of the pfd. solving this equation for ftw yields ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? = 48 2round the frequency lock detector uses a 24-bit frequency threshold register specified in units of picoseconds. thus, the frequency threshold value extends from 0 s to 16.777215 s. it represents the magnitude of the difference in period between the reference and feedback signals at the input to the dpll. for example, if the reference signal is 1.25 mhz and the feedback signal is 1.38 mhz, then the period difference is approximately 75.36 ns (|1/1,250,000 ? 1/1,380,000| 75.36 ns). for example, given that f s = 1 ghz and f dds = 155.52 mhz, then ftw = 437,749,988,378,041 (0x27d028a1dfb9). note that the minimum dac output frequency is 62.5 mhz; therefore, normal operation requires an ftw that yields an output frequency in excess of this lower bound. dac (14-bit) phase offset qd f s frequency t uning word (ftw) dac+ dac? 14 19 48 19 angle to amplitude conversion 48 48 48-bit accumulato r 16 0 8022-018 figure 42. dds block diagram
ad9548 rev. 0 | page 35 of 112 dds phase offset the relative phase of the sinusoid generated by the dds is numerically controlled by adding a phase offset word to the output of the dds accumulator. this is accomplished via the open loop phase offset register (address 030d to address 030e), which is a programmable 16-bit value (phase). the resulting phase offset, ? (in radians), is given by ? ? ? ? ? ? = 16 2 2 phase phase offset and relative time offset are directly related. the time offset is ( phase/2 16 )/f dds (in seconds), where f dds is the output frequency of the dds (in hertz). dac output the output of the digital core of the dds is a time series of numbers representing a sinusoidal waveform. the dac translates the numeric values to an analog signal. the dac output signal appears at two pins that constitute a balanced current source architecture (see figure 43 ). current switch array switch control i fs i scale avdd3 dacoutp dacoutn current mirror gnd 21 22 gnd 18 19 code 08022-019 code 50 ? 50 ? 14 10 i fs (1? ) 2 14 ? 1 code i fs ( ) 2 14 ? 1 figure 43. dac output pins the value of i fs is programmable via the 10-bit dac full-scale current word in the dac current register (address 0213 to address 0214). the value of the 10-bit word (i scale ) sets i fs according to the following formula: () () scale i 16 3 72 a120 fs i += tuning word processing t he frequency tuning words that dictate the output frequency of the dds come from one of three sources (see figure 44 ). ? the free running frequency tuning word register ? the output of the digital loop filter ? the output of the tuning word history processor 08022-070 tuning word history processor tuning word history free-run tuning word tuning word update from digital loop filter to dds tuning word routing control tuning word clamp lower tuning word upper tuning word figure 44. tuning word processing when the dpll is in free-run mode, the dds tuning word is the value stored in the free running frequency tuning word register (address 0300 to address 0305). when the dpll is operating normally (closed loop), the dds tuning word comes from the output of the digital loop filter, which changes dynamically in order to maintain phase lock with the input reference signal (assuming that the device has not performed an automatic switch to holdover mode). when the dpll is in holdover mode, the dds tuning word depends on a historical record of past tuning words during the time that the dpll operated in closed-loop mode. however, regardless of the operating mode, the dds output frequency is ultimately subject to the boundary conditions imposed by the frequency clamp logic, as explained in the frequency clamp section. frequency clamp the user controls the frequency clamp boundaries via the pull- in range limits registers (address 0307 to address 030c). these registers allow the user to fix the dds output frequency between an upper and lower bound with a granularity of 24 bits. note that these upper and lower bounds apply regardless of the frequency tuning word that appears at the input to the dds. the register value relates to the absolute upper or lower frequency bound (f clamp ) as f clamp = f s (n /2 24 ) where n is the value stored in the upper- or lower-limit register,and f s is the system sample rate. even though the frequency clamp limits put a bound on the dds output frequency, the dpll is still free to steer the dds frequency within the clamp limits. the default register values set the clamp range from 0 hz (dc) to f s , effectively eliminating the frequency clamp functionality until the user alters the register values. frequency tuning word history the ad9548 has the ability to track the history of the tuning word samples generated by the dpll digital loop filter output. it does so by periodically computing the average tuning word value over a user-specified interval. the user programs the interval via the 24-bit history accumulation timer register (address 0318 to address 031a). this 24-bit value represents a time interval (t avg ) in milliseconds that extends from 1 ms to a maximum of 4:39:37.215 (hr:min:sec).
ad9548 rev. 0 | page 36 of 112 note that history accumulation timer = 0 should not be programmed because it may cause improper device operation. the control logic performs a calculation of the average tuning word during the t avg interval and stores the result in the holdover history register (address 0d14 to address 0d19). computation of the average for each t avg interval is independent of the previous interval (that is, the average is a memoryless average as opposed to a true moving average). in addition, at the end of each t avg interval, the device generates an internal strobe pulse. the strobe pulse sets the history updated bit in the irq monitor register (assuming the bit is enabled via the irq mask register). furthermore, the strobe pulse is available as an output signal via the multifunction pins (see the multifunction pins (m0 to m7) section). history accumulation begins whenever the device switches to a new reference. by default, the device clears any previous history when it switches to a new reference. furthermore, the user can clear the tuning word history under software control via register 0a03, bit 2, or under hardware control via the multifunction pins (see the multifunction pins (m0 to m7) section). however, the user has the option of programming the device to retain (rather than clear) the old history by setting the persistent history bit (register 031b, bit 3). whenever the tuning word history is nonexistent (that is, after a power-up, reset, or switchover to a new reference with the persistent history bit cleared), the device waits for the history accumulation timer (t avg ) to expire before storing the first history value in the holdover history register. in cases where t avg is quite large (4? hours, for example), a problem arises in that the first averaged result does not become available until the full t avg interval passes. thus, it is possible that as much as 4? hours can elapse before the first averaged result is available. if the device has to switch to holdover mode during this time, a tuning word history is not available. to alleviate this problem, the user has access to the incremental average bits in the history mode register (register 031b, bits[2:0]). if the history has been cleared, then this 3-bit value, k (0 k 7), specifies the number of intermediate averages to take during the first, and only the first, t avg interval. when k = 0, no intermediate averages are calculated; therefore, the first average occurs after interval t avg (the default operating mode). however, if k = 4, for example, four intermediate averages are taken during the first t avg interval. these average computations occur at t avg /16, t avg /8, t avg /4, t avg /2, and t avg (notice that the denominator exhibits a sequence of powers of 2 beginning with t avg /2 k ). the calcu- lation of intermediate averages occurs only during the first t avg interval. all subsequent average computations occur at evenly spaced intervals of t avg . loop control state machine the loop control state machine is responsible for monitoring, initiating, and sequencing changes to the dpll loop. generally, it automatically controls the transition between input references and the entry and exit of holdover mode. in controlling loop state changes, the state machine also arbitrates the application of new loop filter coefficients, divider settings, and phase detector offsets based on the profile settings. the user can manually force the device into holdover or free-run mode via the loop mode register (address 0a01), as well as force the selection of a specific input reference. switchover switchover occurs when the loop controller switches directly from one input reference to another. functionally, the ad9548 handles a reference switchover by briefly entering holdover mode and then immediately recovering. during the switchover event, however, the ad9548 preserves the status of the lock detectors to avoid phantom unlock indications. holdover the holdover state of the dpll is an open-loop operating mode. that is, the device no longer operates as a closed-loop system. instead, the output frequency remains constant and is dependent on the device programming and availability of tuning word history. if a tuning word history exists (see the frequency tuning word history section), then the holdover frequency is the average frequency just prior to entering the holdover state. if there is no tuning word history, then the holdover frequency depends on the state of the single sample fallback bit in the history mode register (register 031b, bit 4). if the single sample fallback bit is logic 0, then the holdover frequency is the frequency defined in the free running frequency tuning word register (address 0300 to address 0305). if the single sample fallback bit is logic 1, then the holdover frequency is the last instantaneous frequency output by the dds just prior to the device entering holdover mode (note that this is not the average frequency prior to holdover). the initial holdover frequency accuracy depends on the loop bandwidth of the dpll and the time elapsed to compute a tuning word history. the longer the historical average, the more accurate the initial holdover frequency (assuming a drift-free system clock). furthermore, the stability of the system clock establishes the stability and long-term accuracy of the holdover output frequency. another consideration is the 48-bit frequency tuning resolution of the dds and its relationship to fractional frequency error, f o /f o , as follows: o s o o f f f f 49 2 = where, f s is the sample rate of the output dac, and f o is the dds output frequency.
ad9548 rev. 0 | page 37 of 112 system clock period the worst-case scenario is maximum f s (1 ghz) and minimum f o (62.5 mhz), which yields f o /f o = 2.8 10 ?14 , less than one part in 10 trillion. many of the user-programmable parameters of the ad9548 have absolute time units. to make this possible, the ad9548 requires a priori knowledge of the period of the system clock. to accom- modate this requirement, the user programs the 21-bit nominal system clock period in the nominal sysclk period register (address 0106 to address 0108). the contents of this register reflect the actual period of the system clock in femtoseconds. the user must properly program this register to ensure proper operation of the device because many of its subsystems rely on this value. recovery from holdover when in holdover and a valid reference becomes available, the device exits holdover operation. the loop state machine restores the dpll to closed-loop operation, locks to the selected reference, and sequences the recovery of all the loop parameters based on the profile settings for the active reference. note that, if the user holdover bit (register 0a01, bit 6) is set, the device does not automatically exit holdover when a valid reference is available. however, automatic recovery can occur after clearing the user holdover bit. system clock details a block diagram of the system clock appears in figure 45 . the signal at the sysclkx input pins becomes the internally buffered dac sampling clock (f s ) via one of three paths. system clock inputs functional description ? high frequency direct (hf) the system clock circuit provides a low jitter, stable, high frequency clock for use by the rest of the chip. the user has the option of directly driving the sysclkx inputs with a high frequency clock source at the desired system clock rate. alternatively, the sysclkx input can be configured to operate in conjunction with the internal sysclk pll. the sysclk pll can synthesize the system clock by means of a crystal resonator connected across the sysclkx input pins or by means of direct application of a low frequency clock source. ? low frequency synthesized (lf) ? crystal resonator synthesized (xtal) note that both the lf and xtal paths require the use of the sysclk pll (see the sysclk pll multiplier section). the main purpose of the hf path is to allow the direct use of a high frequency (500 mhz to 1 ghz) external clock source for clocking the ad9548. this path is optimized for high frequency and low noise floor. note that the hf input also provides a path to sysclk pll (see the sysclk pll multiplier section), which includes an input divider (m) programmable for divide- by -1, -2, -4, or -8. the purpose of the divider is to limit the frequency at the input to the pll to less than 150 mhz (the maximum pfd rate). the sysclkx inputs are internally biased to a dc level of ~1 v. take care to ensure that any external connections do not disturb the dc bias because this may significantly degrade performance. generally, the recommendation is that the sysclkx inputs be ac-coupled to the signal source (except when using a crystal resonator). 2 n vco calibration lock detect system clock m loop filter sysclkn sysclkp sysclk_vreg sysclk_lf hf xtal lf 48 52 53 49 pfd and charge pump 08022-020 figure 45. system clock block diagram
ad9548 rev. 0 | page 38 of 112 the lf path permits the user to provide an lvpecl, lvds, cmos, or sinusoidal low frequency clock for multiplication by the integrated sysclk pll. the lf path handles input frequencies from 3.5 mhz up to 100 mhz. however, when using a sinusoidal input signal, it is best to use a frequency in excess of 20 mhz. otherwise, the resulting low slew rate can lead to substandard noise performance. note that the lf path includes an optional 2 frequency multiplier to double the rate at the input to the sysclk pll and potentially reduce the pll in-band noise. however, to avoid exceeding the maximum pfd rate of 150 mhz, using the 2 frequency multiplier is valid only for input frequencies below 125 mhz. t he xtal path enables the connection of a crystal resonator (typically 10 mhz to 50 mhz) across the sysclkx input pins. an internal amplifier provides the negative resistance required to induce oscillation. the internal amplifier expects a 3.2 mm 2.5 mm at cut, fundamental mode crystal with a maximum motional resistance of 100 . the following crystals, listed in alphabetical order, may meet these criteria. note that, whereas these crystals may meet the preceding criteria according to their data sheets, analog devices, inc., does not guarantee their operation with the ad9548 nor does analog devices endorse one crystal manufacturer/supplier over another. ? avx/kyocera cx3225sb ? ecs ecx-32 ? epson/toyocom tsx-3225 ? fox fx3225bs ? ndk nx3225sa ? siward sx-3225 sysclk pll multiplier the sysclk pll multiplier is an integer-n design and relies on an integrated lc tank and vco. it provides a means to convert a low frequency clock input to the desired system clock frequency, f s (900 mhz to 1 ghz). the sysclk pll multiplier accepts input signals between 3.5 mhz and 500 mhz, but frequencies in excess of 150 mhz require the m-divider to ensure compliance with the maximum pfd rate (150 mhz). the pll contains a feedback divider (n) that is programmable for divide values between 6 and 255. the nominal vco gain is 70 mhz/v. lock detector the sysclk pll has a built-in lock detector. register 0100, bit 2 determines whether the lock detector is active. when active (default), the user controls the sensitivity of the lock detector via the lock detect divider bits (register 0100, bits[1:0]). note that 0 must be written to the system clock stability timer (register 0106 to register 0108) whenever the lock detector is disabled (register 0100, bit 2 = 1). the sysclk pll phase detector operates at the pfd rate, which is f vco /n. each pfd sample indicates whether the reference and feedback signals are phase aligned (within a certain threshold range). while the pll is in the process of acquiring a lock condition, the pfd samples typically consist of an arbitrary sequence of in-phase and out-of-phase indications. as the pll approaches complete phase lock, the number of consecutive in-phase pfd samples grows larger. thus, one way of indicating a locked condition is to count the number of consecutive in-phase pfd samples and if it exceeds a certain value, then declare the pll locked. this is exactly the role of the lock detect divider bits. when the lock detector is enabled (register 0100, bit 2 = 0), the lock detect divider bits determine the number of consecutive in-phase decisions required (128, 256, 512, or 1024) before the lock detector declares a locked condition. the default setting is 128. charge pump the charge pump operates in either automatic or manual mode based on the charge pump mode bit (register 0100, bit 6). when register 0100, bit 6 = 0, the ad9548 automatically selects the appropriate charge pump current based on the n-divider value. note that the user cannot control the charge pump current bits (register 0100, bits[5:3]) in automatic mode. when register 0100, bit 6 = 1, the user determines the charge pump current via the charge pump current bits (register 0100, bits[5:3]). the charge pump current varies from 125 a to 1 ma in 125 a steps. the default setting is 500 a. sysclk pll loop filter the ad9548 has an internal second order loop filter that estab- lishes the loop dynamics for input signals between 12.5 mhz and 100 mhz. by default, the device uses the internal loop filter. however, an external loop filter option is available by setting the external loop filter enable bit (register 0100, bit 7). this bypasses the internal loop filter and allows the device to use an externally connected second order loop filter, as shown in figure 46 . sysclk_vreg r1 ad9548 sysclk_lf c1 c2 48 49 0 8022-021 figure 46. external loop filter schematic
ad9548 rev. 0 | page 39 of 112 to determine the external loop filter components, the user decides on the desired open loop bandwidth (f ol ) and phase margin ( ). these parameters allow calculation of the loop filter components, as follows: () ? ? ? ? ? ? ? ? + = sin 1 1 vcocp ol ki nf r1 () () 2 2 tan ol vcocp fn ki c1 = () () () ? ? ? ? ? ? ? ? ? = cos sin1 2 2 ol vcocp fn ki c2 where k vco = 7 10 7 v/ns (typical), i cp is the programmed charge pump current (amperes), n is the programmed feedback divider value, f ol is the desired open-loop bandwidth (in hertz), and is the desired phase margin (in radians). for example, assuming that n = 40, i cp = 0.5 ma, f ol = 400 khz, and = 50, then the loop filter calculations yield r1 = 3.31 k, c1 = 330 pf, and c2 = 50.4 pf. system clock stability timer the system clock stability timer (register 0106 to register 0108) is a 20-bit value programmed in milliseconds. if the programmed timer value is 0, then the timer immediately indicates that it has timed out. if the programmed timer value is a nonzero value and the sysclk pll is enabled, then the timer starts timing when the sysclk pll lock detector indicates lock and times out after the prescribed period. however, when the user disables the sysclk pll, then the timer ignores the sysclk pll lock detector and starts timing as soon as the sysclk pll is disabled. the user can monitor the status of the stability timer via register 0d01, bit 4, via the multifunction pins or via the irq pin. note that the system clock stability timer must be programmed before the sysclk pll is either activated or disabled. sysclk pll calibration when using the sysclk pll, it is necessary to calibrate the lc vco to ensure that the pll can remain locked to the system clock input signal. assuming the presence of either an external sysclk input signal or a crystal resonator, the calibration process executes after the user sets and then clears the calibrate system clock bit in the cal/sync register (register 0a02, bit 0). during the calibration process, the device calibrates the vco amplitude and frequency. the status of the system clock cali- bration process is user accessible via the system clock register (register 0d01, bit 1). it is also available via the irq monitor register (register 0d02, bit 1) provided the status bit is enabled via the irq mask register. when the calibration sequence is complete, the sysclk pll eventually attains a lock condition, at which point the system clock stability timer begins its countdown sequence. expiration of the timer indicates that the sysclk pll is stable, which is reflected in the system clock register (register 0d01, bit 4). note that the monitors/detectors associated with the input references (refa/aa C refd/dd) are internally disabled until the sysclk pll indicates that it is stable. clock distribution the clock distribution block of the ad9548 provides an integrated solution for generating multiple clock outputs based on frequency dividing the dpll output. the distribution output consists of four channels (out0 to out3). each of the four output channels has a dedicated divider and output driver, as appears in figure 47 . q 0 sync control enable n /mode n sync source clkinp out1p out1n out2p out2n out3p out3n out1 out3 out2 out0 clkinn out_rset out0p out0n reset enable 4 4 4 08022-022 figure 47. clock distribution clock input (clkinx) the clock input handles input signals from a variety of logic families (assuming proper terminations and sufficient voltage swing). it also handles sine wave input signals such as those delivered by the dac reconstruction filter. its default operating frequency range is 62.5 mhz to 500 mhz. super-nyquist operation typically, the maximum usable frequency at the dac output is about 45% of the system clock frequency. however, because it is a sampled dac, its output spectrum contains nyquist images. of particular interest are the images appearing in the first nyquist zone (50% to 100% of the sy stem clock frequency). super- nyquist operation takes advantage of these higher frequencies, but this implies that the clkinx input operates in excess of 500 mhz, which is outside of its default operating limits. the clkinx receiver actually consists of two separate receivers: the default receiver and an optional high frequency receiver,
ad9548 rev. 0 | page 40 of 112 which handles input signals up to 800 mhz. to select the high frequency receiver, write a logic 1 to register 0400, bit 4. super-nyquist operation requires a band-pass filter at the dac output instead of the usual low-pass reconstruction filter. super-nyquist operation is viable as long as the image frequency does not exceed the 800 mhz input range of the receiver. furthermore, to provide acceptable jitter performance, which is a consideration for image signals with low amplitude, the signal at the clkinx input must meet the minimum slew rate requirements. clock dividers the output clock distribution dividers are referred to as q0 to q3, corresponding to the out0 to out3 output channels, respectively. each divider is programmable with 30 bits of division depth. the actual divider ratio is one more than the programmed register value; therefore, a register value of 3, for example, results in a divide ratio of 4. thus, each divider offers a range of divide ratios from 1 to 2 30 (1 to 1,073,741,824). with an even divide ratio, the output signal always exhibits a 50% duty cycle. when the clock divider is bypassed (a divide ratio of 1), the output duty cycle is the same as the input duty cycle. odd output divide ratios (excluding 1) exhibit automatic duty cycle correction given by n xn cycleduty output 2 12 ?+ = where n (which must be an odd number) is the divide ratio and x is the normalized fraction of the high portion of the input period (that is, 0 < x < 1). for example, if n = 5 and the input duty cycle is 20% (x = 0.2), then the output duty cycle is 44%. note that, when the user programs an output as noninverting, then the device adjusts the falling edge timing to accomplish the duty cycle correction. conversely, the device adjusts the rising edge timing for an inverted output. output power-down each of the output channels offers independent control of power-down functionality via the distribution settings register (address 0400). each output channel has a dedicated power- down bit for powering down the output driver. however, if all four outputs are powered down, the entire distribution output enters a deep sleep mode. e ven though each channel has a channel power-down control signal, it may sometimes be desirable to power down an output driver while maintaining the dividers synchronization with the other channel dividers. this is accomplished by either of the following methods: ? in cmos mode, use the divider output enable control bit to stall an output. this provides power savings while maintaining dc drive at the output. ? in lvds/lvpecl mode, place the output in tristate mode (this works in cmos mode as well). output enable each of the output channels offers independent control of enable/ disable functionality via the distribution enable register (address 0401). the distribution outputs use synchronization logic to control enable/disable activity to avoid the production of runt pulses and ensure that outputs with the same divide ratios become active/inactive in unison. output mode t he user has independent control of the operating mode of each of the four output channels via the distribution channel modes register (address 0404 to address 0407). the operating mode control includes ? logic family and pin functionality ? output drive strength ? output polarity the three least significant bits of each of the four distribution channel mode registers comprise the mode bits. the mode value selects the desired logic family and pin functionality of an output channel, as given in table 23 . table 23. output channel logic family and pin functionality mode bits 2:0 logic family and pin functionality 000 cmos (both pins) 001 cmos (positive pin); tristate (negative pin) 010 tristate (positive pin); cmos (negative pin) 011 tristate (both pins) 100 lvds 101 lvpecl 110 unused 111 unused regardless of the selected logic family, each is capable of dc operation. however, the upper frequency is limited by the load conditions, drive strength, and impedance matching inherent in each logic family. practical limitations set the maximum cmos frequency to approximately 250 mhz, whereas lvpecl and lvds are capable of 725 mhz. i n addition to the three mode bits, each of the four distribution channel mode registers includes the following control bits: ? polarity invert ? cmos phase invert ? drive strength the polarity invert bit enables the user to choose between normal polarity and inverted polarity. normal polarity is the default state. inverted polarity reverses the representation of logic 0 and logic 1 regardless of the logic family. the cmos phase invert bit applies only when the mode bits select the cmos logic family. in cmos mode, both output pins
ad9548 rev. 0 | page 41 of 112 of the channel have a dedicated cmos driver. by default, both drivers deliver identical signals. however, setting the cmos phase invert bit causes the signal on an outxn pin to be the opposite of the signal appearing on the outxp pin. the drive strength bit allows the user to control whether the output uses weak (0) or strong (1) drive capability (applies to cmos and lvds but not lvpecl). for the cmos family, the strong setting implies normal cmos drive capability, whereas the weak setting implies low capacitive loading and allows for reduced emi. for the lvds family, the weak setting provides 3.5 ma drive current for standard lvds operation, whereas the strong setting provides 7 ma for double terminated or double voltage lvds operation. note that 3.5 ma and 7 ma are the nominal drive current values when using the internal current setting resistor. output current control with an external resistor by default, the output drivers have an internal current setting resistor (3.12 k nominal) that establishes the nominal drive current for the lvds and lvpecl operating modes. instead of using the internal resistor, the user can set the external distribution resistor bit (register 0400, bit 5) and connect an external resistor to the out_rset pin. note that this feature supports an external resistor value of 3.12 k only, allowing for tighter control of the output current than is possible by using the internal current setting resistor. however, if the user elects to use a nonstandard external resistance, the following equations provide the output drive current as a function of the external resistance (r): r i lvds 8325.10 0 = r i lvds 665.21 1 = r i lvpecl 76.24 = the numeric subscript associated with the lvds output current corresponds to the logic state of the drive strength bit in the distribution channel modes register (address 0404 to address 0407). for r = 3.12 k, the equations yield i lvds0 = 3.5 ma, i lvds1 = 7.0 ma, and i lvpecl = 8.0 ma. note that the device maintains a constant 1.238 v (nominal) across the external resistor. clock distribution synchronization a block diagram of the distribution synchronization functionality appears in figure 48 . the synchronization sequence begins with the primary synchronization signal, which ultimately results in delivery of a synchronization strobe to the clock distribution logic. a s indicated, the primary synchronization signal originates from four possible sources. ? direct sync source via the sync distribution bit (register 0a02, bit 1) ? automatic sync source based on frequency or phase lock detection as controlled via the automatic synchronization register (address 0403) ? multifunction pin sync source via one of the multifunction pins (m0 to m7) ? eeprom sync source via the eeprom all four sources of the primary synchronization signal are logic ord, so any one of them can synchronize the clock distribution output at any time. when using the multifunction pins, the synchronization event is the falling edge of the selected signal. when using the sync distribution bit, the user sets and then clears the bit. the synchronization event is the clearing operation; that is, the logic 1 to logic 0 transition of the bit. the primary synchronization signal can synchronize the distri- bution output directly or it can enable a secondary synchronization signal. this functionality depends on the two sync source bits in the distribution synchronization register (register 0402, bits[5:4]). when sync source = 00 (direct), the falling edge of the primary synchronization signal synchronizes the distribution output directly. when sync source = 01, the rising edge of the primary synch- ronization signal triggers the circuitry that detects a rising edge of the active input reference. the detection of the rising edge is what synchronizes the distribution output. when sync source = 10, the rising edge of the primary synch- ronization signal triggers the circuitry that detects a rollover of the dds accumulator (after processing by the dpll feedback divider). this corresponds to the zero crossing of the output of the phase-to-amplitude converter in the dds (less the open- loop phase offset stored in register 030d to register 030e). the detection of the dpll feedback edge is what synchronizes the distribution output.
ad9548 rev. 0 | page 42 of 112 active reference synchr onization (zero delay) active reference synchronization is the term applied to the case when sync source = 01 (register 0402, bits[5:4]). referring to figure 48 , this means that the active reference sync path is active because bit 4 = 1, enabling the lower and gate and disabling the upper and gate. the edge detector in the active reference sync block monitors the rising edges of the active reference (the mux selects the active reference automatically). the edge detector is armed via the primary synchronization signal, which is one of the four inputs to the or gate (typically the direct sync source). as soon as the edge detector is armed, its output goes high, which stalls the output dividers in the clock distribution block. furthermore, once armed, a rising edge from the active reference forces the output of the edge detector low. this restarts the output dividers, thereby synchronizing the clock distribution block. the term zero delay applies because it provides a means to edge align the output signal with the active input reference signal. typically, zero-delay architectures use the output signal in the feedback loop of a pll to track input/output edge alignment. active reference synchronization, however, operates open loop. that is, synchronization of the output via the distribution synchronization logic occurs on a single edge of the active reference. the fact that an active reference edge triggers the falling edge of the synchronization pulse means that the falling edge is asynchronous to the signal that clocks the distribution output dividers (clkinx). therefore, the output clock distribution logic reclocks the internal synchronization pulse to synchronize it with the clkinx signal. this means that the output dividers restart after a deterministic delay associated with the reclocking circuitry. this deterministic delay has two components. the first deterministic delay component is four or five periods of the clkinx signal. the one period uncertainty is due to the unknown position of the asynchronous reference clock edge relative to the clkinx signal. the second deterministic delay component is one output period of the distribution divider. multifunction pin sync source 0 1 register 0402[5] sysclk/4 dpll feedback edge register 0402[4] ref a ref aa ref d ref dd reset edge detect edge detect arm edge detect arm direct sync dpll edge sync active reference sync eeprom sync source primary synchronization signal direct sync source (register 0a02[1]) automatic sync source (register 0403) to clock distribution synchronization control stall dividers sync output distribution 08022-023 to multifunction pin status logic figure 48. output synchronization block diagram
ad9548 rev. 0 | page 43 of 112 the deterministic delay, expressed as t latency in the following equation is a function of the frequency division factor (q n ) of the channel divider associated with the zero-delay channel. t latency = (q n + 4) t clk_in or t latency = (q n + 5) t clk_in in addition to deterministic delay, there is random delay (t prop ) associated with the propagation of the reference signal through the input reference receiver, as well as the propagation of the clock signal through the clock distribution logic. the total delay is t delay = t latency + t prop the user can compensate for t delay by using the phase offset controls of the device to move the edge timing of the distribution output signal relative to the input reference edge. one method is to use the open-loop phase offset registers (address 030d to address 030e) for timing adjustment. however, be sure to use sufficiently small phase increments to make the adjustment. too large a phase step can result in the clock distribution logic missing a clkinx edge, thus ruining the edge alignment process. the appropriate phase increment depends on the transient response of any external circuitry connected between the dacoutx and clkinx pins. the other method is to use the closed-loop phase offset registers (address 030f to address 0315) for timing adjustment. however, be sure to use a sufficiently small phase vs. time profile. changing the phase too quickly can cause the dpll to lose lock, thus ruining the edge alignment process. note that the ad9548 phase slew limit register (address 0316 to address 0317) can be used to limit the rate of change of phase automatically, thereby mitigating the potential loss-of-lock problem. to guarantee synchronization of the output dividers, it is important to make any edge timing adjustments after the synchronization event. furthermore, when making timing adjustments, the distribution outputs can be disabled and then enabled after the adjustment is complete. this prevents the device from generating output clock signals during the timing adjustment process. note that the form of zero-delay synchronization described here does not track propagation time variations within the distribution clock input path or the reference input path (on or off chip) over temperature, supply, and so on. it is strictly a one-time synchronization event. synchronization mask each output channel has dedicated synchronization mask bits (register 0402, bits[3:0]). when the mask bit associated with a particular channel is set, then that channel does not respond to the synchronization signal. this allows the device to operate with the masked channels active and the unmasked channels stalled while they wait for a synchronization pulse.
ad9548 rev. 0 | page 44 of 112 status and control multifunction pins (m0 to m7) the ad9548 has eight digital cmos i/o pins (m0 to m7) that are configurable for a variety of uses. the function of these pins is programmable via the register map. each pin can control or monitor an assortment of internal functions based on the contents of register 0200 to register 0207. to monitor an internal function with a multifunction pin, write a logic 1 to the most significant bit of the register associated with the desired multifunction pin. the value of the seven least significant bits of the register defines the control function, as shown in table 24 . table 24. multifunction pin output functions, register 0200 to register 0207 (bit 7 = 1) bits[6:0] value output function source proxy 0 static logic 0 1 static logic 1 2 system clock divided by 32 3 watchdog timer output 4 eeprom upload in progress register 0d00, bit 0 5 eeprom download in progress register 0d00, bit 1 6 eeprom fault detected register 0d00, bit 2 7 sysclk pll lock detected register 0d01, bit 0 8 sysclk pll calibration in progress register 0d01, bit 1 9 unused 10 unused 11 sysclk pll stable register 0d01, bit 4 12 to 15 unused 16 dpll free running register 0d0a, bit 0 17 dpll active register 0d0a, bit 1 18 dpll in holdover register 0d0a, bit 2 19 dpll in reference switchover register 0d0a, bit 3 20 active reference: phase master register 0d0a, bit 6 21 dpll phase locked register 0d0a, bit 4 22 dpll frequency locked register 0d0a, bit 5 23 dpll phase slew limited register 0d0a, bit 7 24 dpll frequency clamped register 0d0b, bit 7 25 tuning word history available register 0d0b, bit 6 26 tuning word history updated register 0d05, bit 4 27 to 31 unused 32 reference a fault register 0d0c, bit 2 33 reference aa fault register 0d0d, bit 2 bits[6:0] value output function source proxy 34 reference b fault register 0d0e, bit 2 35 reference bb fault register 0d0f, bit 2 36 reference c fault register 0d10, bit 2 37 reference cc fault register 0d11, bit 2 38 reference d fault register 0d12, bit 2 39 reference dd fault register 0d13, bit 2 40 to 47 unused 48 reference a valid register 0d0c, bit 3 49 reference aa valid register 0d0d, bit 3 50 reference b valid register 0d0e, bit 3 51 reference bb valid register 0d0f, bit 3 52 reference c valid register 0d10, bit 3 53 reference cc valid register 0d11, bit 3 54 reference d valid register 0d12, bit 3 55 reference dd valid register 0d13, bit 3 56 to 63 unused 64 reference a active eference register 0d0b, bits[2:0] 65 reference aa active reference register 0d0b, bits[2:0] 66 reference b active reference register 0d0b, bits[2:0] 67 reference bb active reference register 0d0b, bits[2:0] 68 reference c active reference register 0d0b, bits[2:0] 69 reference cc active reference register 0d0b, bits[2:0] 70 reference d active reference register 0d0b, bits[2:0] 71 reference dd active reference register 0d0b, bits[2:0] 72 to 79 unused 80 clock distribution sync pulse register 0d03, bit 3 81 to 127 unused to control an internal function with a multifunction pin, write a logic 0 to the most significant bit of the register associated with the desired multifunction pin. the monitored function depends on the value of the seven least significant bits of the register, as shown in table 25 . table 25. multifunction pin input functions, register 0200 to register 0207 (bit 7 = 0) bits[6:0] value output function destination proxy 0 unused (default) 1 i/o update register 0005, bit 0 2 full power-down register 0a00, bit 0 3 watchdog reset register 0a03, bit 0 4 irq reset register 0a03, bit 1
ad9548 rev. 0 | page 45 of 112 bits[6:0] value output function destination proxy 5 tuning word history reset register 0a03, bit 2 6 to 15 unused 16 holdover register 0a01, bit 6 17 free run register 0a01, bit 5 18 reset incremental phase offset register 0a0c, bit 2 19 increment incremental phase offset register 0a0c, bit 0 20 decrement incremental phase offset register 0a0c, bit 1 21 to 31 unused 32 override reference monitor a register 0a0f, bit 0 33 override reference monitor aa register 0a0f, bit 1 34 override reference monitor b register 0a0f, bit 2 35 override reference monitor bb register 0a0f, bit 3 36 override reference monitor c register 0a0f, bit 4 37 override reference monitor cc register 0a0f, bit 5 38 override reference monitor d register 0a0f, bit 6 39 override reference monitor dd register 0a0f, bit 7 40 to 47 unused 48 force validation timeout a register 0a0e, bit 0 49 force validation timeout aa register 0a0e, bit 1 50 force validation timeout b register 0a0e, bit 2 51 force validation timeout bb register 0a0e, bit 3 52 force validation timeout c register 0a0e, bit 4 53 force validation timeout cc register 0a0e, bit 5 54 force validation timeout d register 0a0e, bit 6 55 force validation timeout dd register 0a0e, bit 7 56 to 63 unused 64 enable out0 register 0401, bit 0 65 enable out1 register 0401, bit 1 66 enable out2 register 0401, bit 2 67 enable out3 register 0401, bit 3 68 enable out0, out1, out2, out3 register 0401, bits[3:0] 69 sync clock distribution outputs register 0a02, bit 1 70 to 127 unused if more than one multifunction pin operates on the same control signal, then internal priority logic ensures that only one multifunction pin serves as the signal source. the selected pin is the one with the lowest numeric suffix. for example, if both m3 and m7 operate on the same control signal, then m3 is used as the signal source and the redundant pins are ignored. at power-up, the multifunction pins can be used to force the device into certain configurations as defined in the initial pin programming section. this functionality, however, is valid only during power-up or following a reset, after which the pins can be reconfigured via the serial programming port or via the eeprom. irq pin the ad9548 has a dedicated interrupt request (irq) pin. the irq pin output mode register (register 0208, bits[1:0]) controls how the irq pin asserts an interrupt based on the value of the two bits, as follows: 00the irq pin is high impedance when deasserted and active low when asserted and requires an external pull-up resistor (this is the default operating mode). 01the irq pin is high impedance when deasserted and active high when asserted and requires an external pull-down resistor. 10the irq pin is logic 0 when deasserted and logic 1 when asserted. 11the irq pin is logic 1 when deasserted and logic 0 when asserted. the ad9548 asserts the irq pin whenever any of the bits in the irq monitor register (address 0d02 to address 0d09) are logic 1. each bit in this register is associated with an internal function capable of producing an interrupt. furthermore, each bit of the irq monitor register is the result of a logical and of the associated internal interrupt signal and the corresponding bit in the irq mask register (address 0209 to address 0210). that is, the bits in the irq mask register have a one-to-one correspondence with the bits in the irq monitor register. whenever an internal function produces an interrupt signal and the associated irq mask bit is set, then the corresponding bit in the irq monitor register is set. the user should be aware that clearing a bit in the irq mask register removes only the mask associated with the internal interrupt signal. it does not clear the corresponding bit in the irq monitor register. the irq pin is the result of a logical or of all the irq monitor register bits. thus, the ad9548 asserts the irq pin so long as any of the irq monitor register bits are logic 1. note that it is possible to have multiple bits set in the irq monitor register. therefore, when the ad9548 asserts the irq pin, it may indicate an interrupt from several different internal functions. the irq monitor register provides the user with a means to interrogate the ad9548 to determine which internal function(s) produced the interrupt.
ad9548 rev. 0 | page 46 of 112 typically, when the ad9548 asserts the irq pin, the user interrogates the irq monitor register to identify the source of the interrupt request. after servicing an indicated interrupt, the user should clear the associated irq monitor register bit via the irq clearing register (address 0a04 to address 0a0b). the bits in the irq clearing register have a one-to-one correspondence with the bits in the irq monitor register. note that the irq clearing register is autoclearing. the irq pin remains asserted until the user clears all of the bits in the irq monitor register that indicate an interrupt. eeprom eeprom overview the ad9548 contains an integrated 2048-byte, electrically erasable, programmable read-only memory (eeprom). the ad9548 can be configured to perform a download at power-up via the multifunction pins (m3 to m7), but uploads and down- loads can also be done on demand via the eeprom control register (address 0e00 to address 0e03). the eeprom provides the ability to upload and download configuration settings to and from the register map. figure 49 shows a functional diagram of the eeprom. it is also possible to collectively clear all of the irq monitor register bits by setting the reset all irqs bit in the reset function register (register 0a03, bit 1). note that this is an autoclearing bit. setting this bit results in deassertion of the irq pin. alternatively, the user can program any of the multifunction pins to clear all irqs. this allows the user to clear all irqs by means of a hardware pin rather than by a serial i/o port operation. register 0e10 to register 0e3f represent a 48-byte scratch pad that enables the user to store a sequence of instructions for transferring data to the eeprom from the device settings portion of the register map. note that the default values for these registers provide a sample sequence for saving/retrieving all of the ad9548 eeprom-accessible registers. figure 49 shows the connectivity between the eeprom and the controller that manages data transfer between the eeprom and the register map. watchdog timer the watchdog timer is a general-purpose programmable timer. to set the timeout period, the user writes to the 16-bit watchdog timer register (address 0211 to address 0212). a value of 0 in this register disables the timer. a nonzero value sets the timeout period in milliseconds, giving the watchdog timer a range of 1 ms to 65.535 sec. the relative accuracy of the timer is approximately 0.1% with an uncertainty of 0.5 ms. the controller oversees the process of transferring eeprom data to and from the register map. there are two modes of operation handled by the controller: saving data to the eeprom (upload mode) or retrieving data from the eeprom (download mode). in either case, the controller relies on a specific instruction set. if enabled, the timer runs continuously and generates a timeout event whenever the timeout period expires. the user has access to the watchdog timer status via the irq mechanism and the multifunction pins (m0 to m7). in the case of the multifunction pins, the timeout event of the watchdog timer is a pulse that lasts 32 system clock periods. eeprom (000 to 7ff) data data data eeprom address pointer m7 m6 m5 m4 m3 register map device settings (0100 to 0a10) scratch pad (0e10 to 0e3f) serial input/output port condition (0e01 [4:0]) scratch pad address pointer device settings address pointer eeprom controller 08022-024 there are two ways to reset the watchdog timer (thereby preventing it from causing a timeout event). the first is by writing a logic 1 to the autoclearing reset watchdog bit in the reset function register (register 0a03, bit 0). alternatively, the user can program any of the multifunction pins to reset the watchdog timer. this allows the user to reset the timer by means of a hardware pin rather than by a serial i/o port operation. figure 49. eeprom fu nctional diagram
ad9548 rev. 0 | page 47 of 112 table 26. eeprom controller instruction set instruction value (hex) instruction type bytes required description 00 to 7f data 3 a data instruction tells the controller to transfer data to or from the device settings part of the register map. a data instru ction requires two additional bytes that together indicate a starting address in the register map. encoded in the data instruction is the number of bytes to transfer, which is one more than the instruction value. 80 i/o update 1 when the controller encounters this instruction while downloading from the eeprom, it issues a soft i/o update (see register 0005 in table 41 ). a0 calibrate 1 when the controller encounters this instruction while downloading from the eeprom, it initiates a system clock cali bration sequence (see register 0a02 in table 120 ). a1 distribution sync 1 when the controller encounters this instruction while downloading from the eeprom, it issues a sync pulse to the output distribution synchronization (see register 0a02 in table 120 ). b0 to cf condition 1 b1 to cf are condition instructions and correspond to condition 1 through condition 31, respectively. b0 is th e null condition instruction. see the eeprom conditional processing section for details. fe pause 1 when the controller encounters this instru ction in the scratch pad while uploading to the eeprom, it resets the scratch pa d address pointer and holds the eeprom address pointer at its last value. this a llows storage of more than one instruction sequence in the eeprom. note that the cont roller does not copy this instruction to the eeprom during upload. ff end 1 when the controller encounters this instru ction in the scratch pad while uploading to the eeprom, it resets both the scra tch pad address pointer and the eeprom address pointer and then enters an idle state. when the controller encounters this instruction while downloading from the eeprom, it resets the eeprom address pointer and then enters an idle state. eeprom instructions table 26 lists the eeprom controller instruction set. the controller recognizes all instruction types whether it is in upload or download mode, except for the pause instruction, which it only recognizes in upload mode. the i/o update, calibrate, distribution sync, and end instruct- tions are mostly self-explanatory. the others, however, warrant further detail, as described in the following paragraphs. d ata instructions are those that have a value from 00 to 7f. a data instruction tells the controller to transfer data between the eeprom and the register map. the controller needs the following two parameters to carry out the data transfer: ? the number of bytes to transfer ? the register map target address the controller decodes the number of bytes to transfer directly from the data instruction itself by adding one to the value of the instruction. for example, the data instruction, 1a, has a decimal value of 26; therefore, the controller knows to transfer 27 bytes (one more than the value of the instruction). whenever the controller encounters a data instruction, it knows to read the next two bytes in the scratch pad because these contain the register map target address. note that, in the eeprom scratch pad, the two registers that comprise the address portion of a data instruction have the msb of the address in the d7 position of the lower register address. the bit weight increases left to right, from the lower register address to the higher register address. furthermore, the starting address always indicates the lowest numbered register map address in the range of bytes to transfer. that is, the controller always starts at the register map target address and counts upward regardless of whether the serial i/o port is operating in i 2 c, spi lsb-first, or spi msb-first mode. as part of the data transfer process during an eeprom upload, the controller calculates a 1-byte checksum and stores it as the final byte of the data transfer. as part of the data transfer process during an eeprom download, however, the controller again calculates a 1-byte checksum value but compares the newly calculated checksum with the one that was stored during the upload process. if an upload/download checksum pair does not match, the controller sets the eeprom fault status bit. if the upload/download checksums match for all data instructions encountered during a download sequence, the controller sets the eeprom complete status bit. condition instructions are those that have a value from b0 to cf. condition instructions b1 to cf represent condition 1 to condition 31, respectively. the b0 condition instruction is
ad9548 rev. 0 | page 48 of 112 special because it represents the null condition (see the eeprom conditional processing section). a pause instruction, like an end instruction, is stored at the end of a sequence of instructions in the scratch pad. when the controller encounters a pause instruction during an upload sequence, it keeps the eeprom address pointer at its last value. this way the user can store a new instruction sequence in the scratch pad and upload the new sequence to the eeprom. the new sequence is stored in the eeprom address locations immediately following the previously saved sequence. this process is repeatable until an upload sequence contains an end instruction. the pause instruction is also useful when used in conjunction with condition processing. it allows the eeprom to contain multiple occurrences of the same register(s), with each occurrence linked to a set of conditions (see the eeprom conditional processing section). eeprom upload to upload data to the eeprom, the user must first ensure that the write enable bit (register 0e00, bit 0) is set. then, on setting the autoclearing save to eeprom bit (register 0e02, bit 0), the controller initiates the eeprom data storage process. uploading eeprom data requires that the user first write an instruction sequence into the scratch pad registers. during the upload process, the controller reads the scratch pad data byte by byte, starting at register 0e10 and incrementing the scratch pad address pointer as it goes until it reaches a pause or end instruction. as the controller reads the scratch pad data, it transfers the data from the scratch pad to the eeprom (byte by byte) and increments the eeprom address pointer accordingly, unless it encounters a data instruction. a data instruction tells the controller to transfer data from the device settings portion of the register map to the eeprom. the number of bytes to transfer is encoded within the data instruction, and the starting address for the transfer appears in the next two bytes in the scratch pad. when the controller encounters a data instruction, it stores the instruction in the eeprom, increments the eeprom address pointer, decodes the number of bytes to be transferred, and increments the scratch pad address pointer. then it retrieves the next two bytes from the scratch pad (the target address) and increments the scratch pad address pointer by 2. next, the controller transfers the specified number of bytes from the register map (beginning at the target address) to the eeprom. when it completes the data transfer, the controller stores an extra byte in the eeprom to serve as a checksum for the transferred block of data. to account for the checksum byte, the controller increments the eeprom address pointer by one more than the number of bytes transferred. note that, when the controller transfers data associated with an active register, it actually transfers the buffered contents of the register (see the buffered/active registers section for details on the difference between buffered and active registers). this allows for the transfer of nonzero autoclearing register contents. note that conditional processing (see the eeprom conditional processing section) does not occur during an upload sequence. eeprom download an eeprom download results in data transfer from the eeprom to the device register map. to download data, the user sets the autoclearing load from eeprom bit (register 0e03, bit 1). this commands the controller to initiate the eeprom download process. during download, the controller reads the eeprom data byte by byte, incrementing the eeprom address pointer as it goes, until it reaches an end instruction. as the controller reads the eeprom data, it executes the stored instructions, which includes transferring stored data to the device settings portion of the register map whenever it encounters a data instruction. note that conditional processing (see the eeprom conditional processing section) is only applicable when downloading. automatic eeprom download following a power-up, an assertion of the reset pin, or a soft reset (register 0000, bit 5 = 1), if fncinit[7:3] 0 (see the initial pin programming section), then the instruction sequence stored in the eeprom executes automatically with condition = fncinit[7:3]. in this way, a previously stored set of register values downloads automatically on power-up or with a hard or soft reset. see the eeprom conditional processing section for details regarding conditional processing and the way it modifies the download process. eeprom conditional processing the condition instructions allow conditional execution of eeprom instructions during a download sequence. during an upload sequence, however, they are stored as is and have no effect on the upload process. note that, during eeprom downloads, the condition instructions themselves and the end instruction always execute unconditionally. conditional processing makes use of two elements: the condition (from condition 1 to condition 31) and the condition tag board. the relationships among the condition, the condition tag board, and the eeprom controller appear schematically in figure 50 .
ad9548 rev. 0 | page 49 of 112 example condition 3 and condition 13 are tagged eeprom eeprom controller upload procedure condition handler download procedure condition tag board 1 6 5 4 3 2 11 10 9 8 7 30 31 24 23 22 21 20 19 18 17 16 15 14 13 12 25 26 27 28 29 if b1 instruction cf, then tag decoded condition exe cu t e/skip instruction(s) scratch pad condition condition = 0e01, bits[4:0] else condition = fncinit, bits[7:3] endif m7 m3 if instruction = b0, then clear all tags fncinit, bits[7:3] register 0e01, bits[4:0] store condition instructions as they are read from the scratch pad. watch for occurrence of condition instructions during download. if {no tags} or {condition = 0} execute instructions else if {condition is tagged} execute instructions else skip instructions endif endif 5 5 5 0 8022-025 if {0e01, bits[4:0] 0} figure 50. eeprom conditional processing the condition is a 5-bit value with 32 possibilities. condition = 0 is the null condition. when the null condition is in effect, the eeprom controller executes all instructions unconditionally. the remaining 31 possibilities, condition = 1 through condition = 31, modify the eeprom controllers handling of a download sequence. the condition originates from one of two sources (see figure 50 ), as follows: ? fncinit, bits[7:3], which is the state of the m3 to m7 multifunction pins at power-up (see the initial pin programming section) ? register 0e01, bits[4:0] if register 0e01, bits[4:0] 0, then the condition is the value stored in register 0e01, bits[4:0]; otherwise, the condition is fncinit, bits[7:3]. note that a nonzero condition present in register 0e01, bits[4:0] takes precedence over fncinit, bits[7:3]. the condition tag board is a table maintained by the eeprom controller. when the controller encounters a condition instruct- tion, it decodes the b1 through cf instructions as condition = 1 through condition = 31, respectively, and tags that particular condition in the condition tag board. however, the b0 condition instruction decodes as the null condition, for which the controller clears the condition tag board, and subsequent download instructions execute unconditionally (until the controller encounters a new condition instruction). during download, the eeprom controller executes or skips instructions depending on the value of condition and the contents of the condition tag board. note, however, that condition instructions and the end instruction always execute unconditionally during download. if condition = 0, then all instructions during download execute unconditionally. if condition 0 and there are any tagged conditions in the condition tag board, then the controller executes instructions only if the condition is tagged. if the condition is not tagged, then the controller skips instructions until it encounters a condition instruction that decodes as a tagged condition. note that the condition tag board allows for multiple conditions to be tagged at any given moment. this conditional processing mechanism enables the user to have one download instruction sequence with many possible outcomes depending on the value of the condition and the order in which the controller encounters condition instructions. table 27 lists a sample eeprom download instruction sequence. it illustrates the use of condition instructions and how they alter the download sequence. the table begins with the assumption that no conditions are in effect. that is, the most recently executed condition instruction is b0 or no conditional instructions have been processed.
ad9548 rev. 0 | page 50 of 112 table 27. eeprom conditional processing example instruction action 0x08 transfer the system clock register contents regardless of the current condition. 0x01 0x00 0xb1 tag condition 1 0x19 transfer the clock distribution register contents only if condition = 1 0x04 0x00 0xb2 tag condition 2 0xb3 tag condition 3 0x07 transfer the reference input register contents only if condition = 1, 2, or 3 0x05 0x00 0x0a calibrate the system clock only if condition = 1, 2, or 3 0xb0 clear the condition tag board 0x80 execute an i/o update regardless of the value of the condition 0x0a calibrate the system clock regardless of the value of the condition storing multiple device setups in eeprom c onditional processing makes it possible to create a number of different device setups, store them in eeprom, and download a specific setup on demand. to do so, first program the device control registers for a specific setup. then, store an upload sequence in the eeprom scratch pad with the following general form: 1. condition instruction (b1 to cf) to identify the setup with a specific condition (1 to 31) 2. data instructions (to save the register contents) along with any required calibrate and/or i/o update instructions 3. pause instruction (fe) with the upload sequence written to the scratch pad, perform an eeprom upload (register 0e02, bit 0). re program the device control registers for the next desired setup. then store a new upload sequence in the eeprom scratch pad with the following general form: 1. condition instruction (b0) 2. the next desired condition instruction (b1 to cf, but different than the one used during the previous upload to identify a new setup) 3. data instructions (to save the register contents) along with any required calibrate and/or i/o update instructions 4. pause instruction (fe) with the upload sequence written to the scratch pad, perform an eeprom upload (register 0e02, bit 0). repeat the process of programming the device control registers for a new setup, storing a new upload sequence in the eeprom scratch pad (step 1 through step 4), and executing an eeprom upload (register 0e02, bit 0) until all of the desired setups have been uploaded to the eeprom. note that, on the final upload sequence stored in the scratch pad, the pause instruction (fe) must be replaced with an end instruction (ff). to download a specific setup on demand, first store the condition associated with the desired setup in register 0e01, bits[4:0]. then perform an eeprom download (register 0e03, bit 1). alternatively, to download a specific setup at power-up, apply the required logic levels necessary to encode the desired condition on the m3 to m7 multifunction pins. then power up the device; an automatic eeprom download occurs. the condition (as established by the m3 to m7 multifunction pins) guides the download sequence and results in a specific setup. keep in mind that the number of setups that can be stored in the eeprom is limited. the eeprom can hold a total of 2048 bytes. each nondata instruction requires one byte of storage. each data instruction, however, requires n + 4 bytes of storage, where n is the number of transferred register bytes and the other four bytes include the data instruction itself (one byte), the target address (two bytes), and the checksum calculated by the eeprom controller during the upload sequence (one byte).
ad9548 rev. 0 | page 51 of 112 serial control port m7 m0 m1 m2 m3 m4 m5 m6 13-bit address space read only region read/write region analog blocks and digital core power-on reset serial control arbiter spi i 2 c eeprom controller 400khz multi- function pin control logic sclk/scl cs/sda sdio sdo eeprom 0 8022-026 figure 51. serial port functional diagram the ad9548 serial control port is a flexible, synchronous serial communications port that provides a convenient interface to many industry-standard microcontrollers and microprocessors. the ad9548 serial control port is compatible with most synchronous transfer formats, including philips i2c, motorola spi, and intel ssr protocols. the serial control port allows read/write access to the ad9548 register map. in spi mode, single or multiple byte transfers are supported. the spi port configuration is programmable via register 0000. this register is integrated into the spi control logic rather than in the register map and is distinct from the i 2 c register 0000. it is also inaccessible to the eeprom controller. a functional diagram of the serial control port, including its relationship to the eeprom, appears in figure 51 . although the ad9548 supports both the spi and i 2 c serial port protocols, only one is active following power-up (as determined by the multifunction pins, m0 to m2, during the startup sequence). that is, the only way to change the serial port protocol is to reset the device (or cycle the device power supply). both protocols use a common set of control pins as shown in figure 52 . ad9548 sclk/scl csb/sda sdo sdio 2 5 4 3 serial control port 08022-027 figure 52. serial control port spi/i2c port selection because the ad9548 supports both spi and i2c protocols, the active serial port protocol depends on the logic state of the three multifunction pins, m0 to m2, at startup. if all three pins are set to logic 0 at startup, then the spi protocol is active. otherwise, the i2c protocol is active with seven different i2c slave address settings based on the startup logic pattern on the m0 to m2 pins (see table 28 ). note that the four msbs of the slave address are hardware coded as 1011. table 28. serial port mode selection m2 m1 m0 serial port mode 0 0 0 spi 0 0 1 i2c (address = 1001001) 0 1 0 i2c (address = 1001010) 0 1 1 i2c (address = 1001011) 1 0 0 i2c (address = 1001100) 1 0 1 i2c (address = 1001101) 1 1 0 i2c (address = 1001110) 1 1 1 i2c (address = 1001111) spi serial port operation pin descriptions the sclk (serial clock) pin serves as the serial shift clock. this pin is an input. sclk synchronizes serial control port read and write operations. the rising edge sclk registers write data bits, and the falling edge registers read data bits. the sclk pin supports a maximum clock rate of 40 mhz. the sdio (serial data input/output) pin is a dual-purpose pin and acts as either an input only (unidirectional mode) or as both an input and an output (bidirectional mode). the ad9548 default spi mode is bidirectional. the sdo (serial data output) pin is useful only in unidirectional i/o mode. it serves as the data output pin for read operations. the cs (chip select) pin is an active low control that gates read and write operations. this pin is internally connected to a 30 k pull-up resistor. when cs is high, the sdo and sdio pins go into a high impedance state. spi mode operation the spi port supports both 3-wire (bidirectional) and 4-wire (unidirectional) hardware configurations and both msb-first and lsb-first data formats. both the hardware configuration
ad9548 rev. 0 | page 52 of 112 and data format features are programmable. by default, the ad9548 uses the bidirectional msb-first mode. the reason that bidirectional is the default mode is so that the user can still write to the device, if it is wired for unidirectional operation, to switch to unidirectional mode. assertion (active low) of the cs pin initiates a write or read operation to the ad9548 spi port. for data transfers of three bytes or fewer (excluding the instruction word), the device supports the cs stalled high mode (see ). in this mode, the table 29 cs pin can be temporarily deasserted on any byte boundary, allowing time for the system controller to process the next byte. cs can be deasserted only on byte boundaries, however. this applies to both the instruction and data portions of the transfer. during stall high periods, the serial control port state machine enters a wait state until all data is sent. if the system controller decides to abort a transfer midstream, then the state machine must be reset by either completing the transfer or by asserting the cs pin for at least one complete sclk cycle (but less than eight sclk cycles). deasserting the cs pin on a nonbyte boundary terminates the serial transfer and flushes the buffer. in the streaming mode (see table 29 ), any number of data bytes can be transferred in a continuous stream. the register address is automatically incremented or decremented. cs must be deasserted at the end of the last byte transferred, thereby ending the stream mode. table 29. byte transfer count w1 w0 bytes to transfer 0 0 1 0 1 2 1 0 3 1 1 streaming mode communication cycleinstruction plus data the spi protocol consists of a two-part communication cycle. the first part is a 16-bit instruction word that is coincident with the first 16 sclk rising edges and a payload. the instruction word provides the ad9548 serial control port with information regarding the payload. the instruction word includes the r/ w bit that indicates the direction of the payload transfer (that is, a read or write operation). the instruction word also indicates the number of bytes in the payload and the starting register address of the first payload byte. write if the instruction word indicates a write operation, the payload is written into the serial control port buffer of the ad9548. data bits are registered on the rising edge of sclk. the length of the transfer (1, 2, or 3 bytes or streaming mode) depends on the w0 and w1 bits (see table 29 ) in the instruction byte. when not streaming, cs can be deasserted after each sequence of eight bits to stall the bus (except after the last byte, where it ends the cycle). when the bus is stalled, the serial transfer resumes when cs is asserted. deasserting the cs pin on a nonbyte boundary resets the serial control port. reserved or blank registers are not skipped over automatically during a write sequence. therefore, the user must know what bit pattern to write to the reserved registers to preserve proper operation of the part. generally, it does not matter what data is written to blank registers, but it is customary to write 0s. most of the serial port registers are buffered (see the buffered/active registers section for details on the difference between buffered and active registers). therefore, data written into buffered registers does not take effect immediately. an additional operation is needed to transfer buffered serial control port contents to the registers that actually control the device. this is accomplished with an i/o update operation, which is performed in one of two ways. one is by writing a logic 1 to register 0005, bit 0 (this bit is self-clearing). the other is to use an external signal via an appropriately programmed multifunction pin. the user can change as many register bits as desired before executing an i/o update. the i/o update operation transfers the buffer register contents to their active register counterparts. read the ad9548 supports the long instruction mode only. if the instruction word indicates a read operation, the next n 8 sclk cycles clock out the data from the address specified in the instruction word. n is the number of data bytes read and depends on the w0 and w1 bits of the instruction word. the readback data is valid on the falling edge of sclk. blank registers are not skipped over during readback. a readback operation takes data from either the serial control port buffer registers or the active registers, as determined by register 0004, bit 0. spi instruction word (16 bits) the msb of the 16-bit instruction word is r/ w , which indicates whether the instruction is a read or a write. the next two bits, w1 and w0, indicate the number of bytes in the transfer (see ). the final 13 bits are the register address (a12 to a0), which indicates the starting register address of the read/write operation (see ). table 29 table 31 spi msb-/lsb-first transfers the ad9548 instruction word and payload can be msb first or lsb first. the default for the ad9548 is msb first. the lsb-first mode can be set by writing a 1 to register 0000, bit 6. immed- iately after the lsb-first bit is set, subsequent serial control port operations are lsb first. when msb-first mode is active, the instruction and data bytes must be written from msb to lsb. multibyte data transfers in msb-first format start with an instruction byte that includes the register address of the most significant payload byte. subsequent data bytes must follow in order from high address to low address. in msb-first mode, the serial control port internal
ad9548 rev. 0 | page 53 of 112 address generator decrements for each data byte of the multi- byte transfer cycle. when register 0000, bit 6 = 1 (lsb first), the instruction and data bytes must be written from lsb to msb. multibyte data transfers in lsb-first format start with an instruction byte that includes the register address of the least significant payload byte followed by multiple data bytes. the serial control port internal byte address generator increments for each byte of the multibyte transfer cycle. for multibyte msb-first (default) i/o operations, the serial control port register address decrements from the specified starting address toward address 0000. for multibyte lsb-first i/o operations, the serial control port register address increments from the starting address toward address 1fff. unused addresses are not skipped during multibyte i/o operations; therefore, the user should write the default value to a reserved register and 0s to unmapped registers. note that it is more efficient to issue a new write command than to write the default value to more than two consecutive reserved (or unmapped) registers. table 30. streaming mode (no addresses are skipped) write mode address direction stop sequence lsb first increment 0x0000 ... 0x1fff msb first decrement 0x1fff ... 0x0000 table 31. serial control port, 16-bit instruction word, msb first msb lsb i15 i14 i13 i12 i11 i10 i9 i8 i7 i6 i5 i4 i3 i2 i1 i0 r/ w w1 w0 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 cs sclk don't care sdio a12 w0 w1 r/w a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 don't care don't care don't care 16-bit instruction header register (n) data register (n ? 1) data 0 8022-029 figure 53. serial control port writemsb firs t, 16-bit instruction, two bytes of data cs sclk sdio sdo register (n) data 16-bit instruction header register (n ? 1) data register (n ? 2) data register (n ? 3) data a12 w0w1 r/w a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 don't care don't care don't care don't care d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 08022-030 figure 54. serial control port readmsb firs t, 16-bit instruction, four bytes of data t s don't care don't care w1w0a12a11a10a9a8a7a6a5d4d3d2d1d0 don't care don't care r/w t ds t dh t hi t lo t clk t c cs sclk sdio 0 8022-031 figure 55. serial control port writemsb firs t, 16-bit instruction, timing measurements
ad9548 rev. 0 | page 54 of 112 data bit n ? 1 data bit n cs sclk sdio sdo t dv 08022-032 figure 56. timing diagram for serial control port register read cs sclk don't care don't care 16-bit instruction header register (n) data register (n + 1) data sdio don't care don't care a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 d1d0r/w w1 w0 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7 0 8022-033 figure 57. serial control port writelsb firs t, 16-bit instruction, two bytes of data cs sclk sdio t hi t lo t clk t s t ds t dh t c bit n bit n + 1 08022-034 figure 58. serial control port timingwrite table 32. serial control port timing parameter description t ds setup time between data and the rising edge of sclk t dh hold time between data and the rising edge of sclk t clk period of the clock t s setup time between the cs falling edge and the sclk rising edge (start of the communication cycle) t c setup time between the sclk rising edge and cs rising edge (end of the communication cycle) t hi minimum period that sclk should be in a logic high state t lo minimum period that sclk should be in a logic low state t dv sclk to valid sdio and sdo (see figure 56 )
ad9548 rev. 0 | page 55 of 112 i2c serial port operation the i 2 c interface has the advantage of requiring only two control pins and is a de facto standard throughout the i 2 c industry. however, its disadvantage is programming speed, which is 400 kbps maximum. the ad9548 i2c port design is based on the i2c fast mode standard from philips, so it supports both the 100 khz standard mode and 400 khz fast mode. fast mode imposes a glitch tolerance requirement on the control signals. that is, the input receivers ignore pulses of less than 50 ns duration. the ad9548 i2c port consists of a serial data line (sda) and a serial clock line (scl). in an i2c bus system, the ad9548 is connected to the serial bus (data bus sda and clock bus scl) as a slave device; that is, no clock is generated by the ad9548. the ad9548 uses direct 16-bit memory addressing instead of traditional 8-bit memory addressing. the ad9548 allows up to seven unique slave devices to occupy the i 2 c bus. these are accessed via a 7-bit slave address transmitted as part of an i 2 c packet. only the device with a matching slave address responds to subsequent i 2 c commands. the device slave address is 1001xxx (the three right bits are determined by the m0 to m2 pins). the four msbs (1001) are hard-wired, while the three lsbs (xxx, determined by the m0 to m2 pins) are programmable via the power-up state of the multifunction pins (see the initial pin programming section). i 2 c bus characteristics a summary of the various i 2 c protocols appears in table 33 . table 33. i 2 c bus abbreviation definitions abbreviation definition s start sr repeated start p stop a acknowledge a nonacknowledge w write r read the transfer of data is shown in figure 59 . one clock pulse is generated for each data bit transferred. the data on the sda line must be stable during the high period of the clock. the high or low state of the data line can only change when the clock signal on the scl line is low. data line stable; data valid change of data allowed 08022-035 s d a scl figure 59. valid bit transfer start/stop functionality is shown in figure 60 . the start condition is characterized by a high-to-low transition on the sda line while scl is high. the start condition is always generated by the master to initialize a data transfer. the stop condition is characterized by a low-to-high transition on the sda line while scl is high. the stop condition is always generated by the master to terminate a data transfer. every byte on the sda line must be eight bits long. each byte must be followed by an acknowledge bit; bytes are sent msb first. sda start condition stop condition scl s p 0 8022-036 figure 60. start and stop conditions 12 89 12 3 to 7 3 to 7 89 10 sd a scl s msb ack from slave-receiver ack from slave-receiver p 08022-037 figure 61. acknowledge bit
ad9548 rev. 0 | page 56 of 112 the acknowledge bit (a) is the ninth bit attached to any 8-bit data byte. an acknowledge bit is always generated by the receiving device (receiver) to inform the transmitter that the byte has been received. it is done by pulling the sda line low during the ninth clock pulse after each 8-bit data byte. the nonacknowledge bit ( a ) is the ninth bit attached to any 8-bit data byte. a nonacknowledge bit is always generated by the receiving device (receiver) to inform the transmitter that the byte has not been received. it is done by leaving the sda line high during the ninth clock pulse after each 8-bit data byte. data transfer process the master initiates data transfer by asserting a start condition. this indicates that a data stream follows. all i2c slave devices connected to the serial bus respond to the start condition. the master then sends an 8-bit address byte over the sda line, consisting of a 7-bit slave address (msb first) plus an r/ w bit. this bit determines the direction of the data transfer, that is, whether data is written to or read from the slave device (0 = write, 1 = read). the peripheral whose address corresponds to the transmitted address responds by sending an acknowledge bit. all other devices on the bus remain idle while the selected device waits for data to be read from or written to it. if the r/ w bit is 0, the master (transmitter) writes to the slave device (receiver). if the r/ w bit is 1, the master (receiver) reads from the slave device (transmitter). the format for these commands is described in the data transfer format section data is then sent over the serial bus in the format of nine clock pulses, one data byte (eight bits) from either master (write mode) or slave (read mode) followed by an acknowledge bit from the receiving device. the number of bytes that can be transmitted per transfer is unrestricted. in write mode, the first two data bytes immediately after the slave address byte are the internal memory (control registers) address bytes, with the high address byte first. this addressing scheme gives a memory address of up to 2 16 ? 1 = 65,535. the data bytes after these two memory address bytes are register data written to or read from the control registers. in read mode, the data bytes after the slave address byte are register data written to or read from the control registers. when all data bytes are read or written, stop conditions are established. in write mode, the master (transmitter) asserts a stop condition to end data transfer during the 10 th clock pulse following the acknowledge bit for the last data byte from the slave device (receiver). in read mode, the master device (receiver) receives the last data byte from the slave device (transmitter) but does not pull sda low during the ninth clock pulse. this is known as a nonacknowledge bit. by receiving the nonacknowledge bit, the slave device knows the data transfer is finished and enters idle mode. the master then takes the data line low during the low period before the 10 th clock pulse, and high during the 10 th clock pulse to assert a stop condition. a start condition can be used in place of a stop condition. furthermore, a start or stop condition can occur at any time, and partially transferred bytes are discarded. 12 89 12 3 to 7 3 to 7 891 0 ack from slave-receiver ack from slave-receiver sd a scl s msb p 08022-038 figure 62. data transfer process (master write mode, 2-byte transfer) 12 89 12 3 to 7 3 to 7 8910 ack from master-receiver non-ack from master-receiver sd a scl s p 08022-039 figure 63. data transfer process (m aster read mode, 2-byte transfer)
ad9548 rev. 0 | page 57 of 112 data transfer format write byte formatthe write byte protocol is used to write a register address to the ram starting from the specified ram addres s. s slave address w a ram address high byte a ram address low byte a ram data 0 a ram data 1 a ram data 2 a p send byte formatthe send byte protocol is used to set up the register address for subsequent reads. s slave address w a ram address high byte a ram address low byte a p receive byte formatthe receive byte protocol is used to read the data byte(s) from ram starting from the current address. s slave address r a ram data 0 a ram data 1 a ram data 2 a p read byte formatthe combined format of the send byte and the receive byte. s slave address w a ram address high byte a ram address low byte a sr slave address r a ram data 0 a ram data 1 a ram data 2 a p i2c serial port timing ss r p s s d a scl t sp t hd; sta t su; sta t su; dat t hd; dat t hd; sta t hi t lo t su; sto t buf t r t f t r t f 08022-040 figure 64. i2c serial port timing table 34. ic timing definitions parameter description f scl serial clock t buf bus free time between stop and start conditions t hd; sta repeated hold time start condition t su; sta repeated start condition setup time t su; sto stop condition setup time t hd; dat data hold time t su; dat date setup time t lo scl clock low period t hi scl clock high period t r minimum/maximum receive scl and sda rise time t f minimum/maximum receive scl and sda fall time t sp pulse width of voltage spikes that must be suppressed by the input filter
ad9548 rev. 0 | page 58 of 112 i/o programming registers the register map spans an address range from 0x0000 through 0x0e3f (0 to 3647, decimal). each address provides access to 1 byte (eight bits) of data. each individual register is identified by its four-digit hexadecimal address (for example, register 0a10). in some cases, a group of addresses collectively define a register (for example, the irq mask register consists of register 0209, register 020a, register 020b, register 020c, register 020d, register 020e, register 020f, and register 0210). in general, when a group of registers defines a control parameter, the lsb of the value resides in the d0 position of the register with the lowest address. the bit weight increases right to left, from the lowest register address to the highest register address. for example, the default value of the incremental phase lock offset step size register (address 0314 to address 0315) is the 16-bit hexadecimal number, 0x03e8 (not 0xe803). note that the eeprom storage sequence registers (address 0e10 to address 0e3f) are an exception to the above convention (see the eeprom instructions section). buffered/active registers there are two broad categories of registers in the ad9548, buffered and active (see figure 65 ). buffered registers are those that can be written to directly from the serial port. they do not need an i/o update to apply their contents to the internal device functions. in contrast, active registers require an i/o update to transfer data between the buffer registers and the internal device functions. in operation, the user programs as many buffer registers as desired and then issues an i/o update. the i/o update occurs by writing to register 0005, bit 0 = 1 (or by the external application of the necessary logic level to one of the multifunction pins previously programmed as an i/o update input). the contents of buffer registers connected directly to the internal device functions affect those functions immediately. the contents of buffer registers that connect to active registers do not affect the internal device functions until the i/o update event occurs. an s or c in the opt column of the register map identifies a register as an active register (otherwise, it is a buffer register). an s entry means that the i/o update signal to the active register is synchronized with the serial port clock or with an input signal driving one of the multifunction pins. on the other hand, a c entry means that the i/o update signal to the active register is synchronized with a clock signal derived from the internal system clock (f s /32), as shown in figure 65 . when reading back a register that has both buffered and active contents, the user can use register 0004, bit 0 to select whether to read back the buffer or active contents. readback of the active contents occurs when register 0004, bit 0 = 0, whereas readback of the buffer contents occurs when register 0004, bit 0 = 1. note that a read-only active register requires an i/o update before reading its contents. active c registers active s registers i/o update to internal device functions buffer registers from multifunction pin logic serial control port f s /32 edge detect cs/sda sclk/scl sdio sdo 5 3 4 2 08022-041 figure 65. buffered and active registers autoclear registers an a in the opt column of the register map identifies an auto- clear register. typically, the active value for an autoclear register takes effect following an i/o update. the bit is cleared by the internal device logic upon comple tion of the prescribed action.
ad9548 rev. 0 | page 59 of 112 register access restrictions read and write access to the register map may be restricted depending on the register in question, the source and direction of access, and the current state of the device. each register can be classified into one or more access types. when more than one type applies, the most restrictive condition that applies at the moment is used. whenever access is denied to a register, all attempts to read the register return a 0 byte, and all attempts to write to the register are ignored. access to nonexistent registers is handled in the same way as for a denied register. regular access registers with regular access do not fall into any other category. both read and write access to registers of this type can be from either the serial ports or eeprom controller. however, only one of these sources can have access to a register at any given time (access is mutually exclusive). whenever the eeprom controller is active, either in load or store mode, it has exclusive access to these registers. read-only access an r in the opt column of the register map identifies read-only registers. access is available at all times, including when the eeprom controller is active. exclusion from eeprom access an e in the opt column of the register map identifies a register with contents that are inaccessible to the eeprom. that is, the contents of this type of register cannot be transferred directly to the eeprom or vice versa. note that read-only registers (r) are inaccessible to the eeprom, as well.
ad9548 rev. 0 | page 60 of 112 register map table 35. addr opt name d7 d6 d5 d4 d3 d2 d1 d0 def serial port control and part identification 0000 e spi control unidirec- tional lsb first/ inc addr soft reset long instruction unused 10 0000 dup i2c control unused soft reset unused 00 0001 e reserved unused 0002 r reserved silicon revision number 01 0003 r device id 48 0004 e readback unused read buffer register 00 0005 a, e i/o update unused i/o update 00 system clock 0100 s external loop filter enable charge pump mode (auto/ man) charge pump current [2:0] lock detect timer disable lock detect divider [1:0] 18 0101 s n-divider [7:0] 28 0102 s unused m-divider reset m-divider [1:0] 2 frequency multiplier enable pll enable sysclk reference select [1:0] 45 0103 c nom sysclk period nominal system clock period (femtoseconds) [15:0] [1 ns @ 1 ppm accuracy] 40 0104 c 42 0105 c unused nominal system clock period [20:16] 0f 0106 c system clock stability system clock stability period (milliseconds) [15:0] 01 0107 c 00 0108 c unused system clock stability period (milliseconds) [19:16] 00 general configuration 0200 s m0 m0 in/out m0 function [6:0] 00 0201 s m1 m1 in/out m1 function [6:0] 00 0202 s m2 m2 in/out m2 function [6:0] 00 0203 s m3 m3 in/out m3 function [6:0] 00 0204 s m4 m4 in/out m4 function [6:0] 00 0205 s m5 m5 in/out m5 function [6:0] 00 0206 s m6 m6 in/out m6 function [6:0] 00 0207 s m7 m7 in/out m7 function [6:0] 00 0208 c irq pin output mode unused irq pin output mode [1:0] 00 0209 c irq mask unused sysclk unlocked sysclk locked unused unused sysclk cal complete sysclk cal started 00 020a c unused distribution sync watchdog timer eeprom fault eeprom complete 00 020b c switching closed freerun holdover freq unlocked freq locked phase unlocked phase locked 00 020c c unused history updated frequency unclamped frequency clamped phase slew unlimited phase slew limited 00 020d c ref aa new profile ref aa validated ref aa fault cleared ref aa fault ref a new profile ref a validated ref a fault cleared ref a fault 00 020e c ref bb new profile ref bb validated ref bb fault cleared ref bb fault ref b new profile ref b validated ref b fault cleared ref b fault 00 020f c ref cc new profile ref cc validated ref cc fault cleared ref cc fault ref c new profile ref c validated ref c fault cleared ref c fault 00
ad9548 rev. 0 | page 61 of 112 addr opt name d7 d6 d5 d4 d3 d2 d1 d0 def 0210 c ref dd new profile ref dd validated ref dd fault cleared ref dd fault ref d new profile ref d validated ref d fault cleared ref d fault 00 0211 c watchdog timer watchdog timer (ms) [15:0] [up to 65.5 sec] 00 0212 c 00 0213 s dac current dac full-scale current [7:0] ff 0214 s dac shutdown unused dac full-scale current [9:8] 01 dpll 0300 c free running frequency tuning word free running frequency tuning word [47:0] 00 0301 c 00 0302 c 00 0303 c 00 0304 c 00 0305 c 00 0306 a, c update tw unused update tw 00 0307 c pull-in range limits pull-in range lower limit [23:0] 00 0308 c 00 0309 c 00 030a c pull-in range upper limit [23:0] ff 030b c ff 030c c ff 030d c open loop phase offset dds phase offset word [15:0] 00 030e c 00 030f c closed loop phase offset fixed phase lock offset [39:0] (picoseconds; signed) 00 0310 c 00 0311 c 00 0312 c 00 0313 c 00 0314 c incremental phase lock offset step size [15:0] (picoseconds) e8 0315 c 03 0316 c phase slew limit phase slew rate limit [15:0] (ns/sec) 00 0317 c 00 0318 c history accumulation timer history accumulation timer [23:0] (milliseconds) 30 0319 c 75 031a c 00 031b c history mode unused single sample fallback persistent history incremental average [2:0] 00 clock distribution output 0400 s distribution settings unused external distribution resistor receiver mode out3 power- down out2 power- down out1 power- down out0 power- down 00 0401 s distribution enable unused out3 enable out2 enable out1 enable out0 enable 00 0402 s distribution synchroniza- tion unused sync source [1:0] out3 sync mask out2 sync mask out1 sync mask out0 sync mask 00 0403 c automatic synchroniza- tion unused automatic sync mode [1:0] 00 0404 s distribution channel modes unused out0 cmos phase invert out0 polarity invert out0 drive strength out0 mode 03 0405 s unused out1 cmos phase invert out1 polarity invert out1 drive strength out1 mode 03
ad9548 rev. 0 | page 62 of 112 addr opt name d7 d6 d5 d4 d3 d2 d1 d0 def 0406 s unused out2 cmos phase invert out2 polarity invert out2 drive strength out2 mode 03 0407 s unused out3 cmos phase invert out3 polarity invert out3 drive strength out3 mode 03 0408 s distribution channel dividers q0 [23:0] 00 0409 s 00 040a s 00 040b s unused q0 [29:24] 00 040c s q1 [23:0] 00 040d s 00 040e s 00 040f s unused q1 [29:24] 00 0410 s q2 [23:0] 00 0411 s 00 0412 s 00 0413 s unused q2 [29:24] 00 0414 s q3 [23:0] 00 0415 s 00 0416 s 00 0417 s unused q3 [29:24] 00 reference inputs 0500 s reference power-down ref dd power- down ref d power- down ref cc power- down ref c power- down ref bb power- down ref b power- down ref aa power- down ref a power- down 00 0501 s reference logic family ref bb logic family [1:0] ref b logic family [1:0] re f aa logic family [1:0] ref a logic family [1:0] 00 0502 s ref dd logic family [1:0] ref d logic family [1:0] ref cc logic family [1:0] ref c logic family [1:0] 00 0503 c manual reference profile selection enable ref aa manual profile ref aa manual profile [2:0] enable ref a manual profile ref a manual profile [2:0] 00 0504 c enable ref bb manual profile ref bb manual profile [2:0] enable ref b manual profile ref b manual profile [2:0] 00 0505 c enable ref cc manual profile ref cc manual profile [2:0] enable ref c manual profile ref c manual profile [2:0] 00 0506 c enable ref dd manual profile ref dd manual profile [2:0] enable ref d manual profile ref d manual profile [2:0] 00 0507 c phase build- out switching unused phase master threshold priority [2:0] 00 profile 0 0600 priorities unused promoted prio rity [2:0] selection priority [2:0] 00 0601 reference period nominal period (femtoseconds) [47:0] (up to 1.125 sec) 00 0602 00 0603 00 0604 00 0605 00 0606 00 0607 unused nominal period [49:48] 00 0608 tolerance inner tolerance (1/tolerance) [15:0] (removes fault status; 10% down to 1 ppm) 00 0609 00 060a unused inner tolerance [19:16] 00 060b outer tolerance (1/tolerance) [15:0] (i ndicates fault status; 10% down to 1 ppm) 00 060c 00 060d unused outer tolerance [19:16] 00 060e validation validation timer (milliseconds) [15:0] (up to 65.5 sec) 00
ad9548 rev. 0 | page 63 of 112 addr opt name d7 d6 d5 d4 d3 d2 d1 d0 def 060f 00 0610 redetect timeout redetect timer (milliseconds) [15:0] [up to 65.5 seconds] 00 0611 00 0612 digital loop filter coefficients alpha-0 linear [15:0] 00 0613 00 0614 alpha-2 exponent [1:0] alpha-1 exponent [5:0] 00 0615 beta-0 linear [6:0] alpha-2 exponent [2] 00 0616 beta-0 linear [14:7] 00 0617 unused beta-1 exponent [4:0] beta-0 linear [16:15] 00 0618 gamma-0 linear [15:0] 00 0619 00 061a unused gamma-1 exponent [4:0] gamma-0 linear [16] 00 061b delta-0 linear [7:0] 00 061c delta-1 exponent [0] delta-0 linear [14:8] 00 061d alpha-3 exponent [3:0] delta-1 exponent [4:1] 00 061e frequency multiplica- tion r [23:0] 00 061f 00 0620 00 0621 unused r [29:24] 00 0622 s [23:0] 00 0623 00 0624 00 0625 unused s [29:24] 00 0626 v [7:0] 00 0627 u [3:0] unused v [9:8] 00 0628 unused u [9:4] 00 0629 lock detectors phase lock threshold (p icoseconds) [15:0] 00 062a 00 062b phase lock fill rate [7:0] 00 062c phase lock drain rate [7:0] 00 062d frequency lock threshol d (picoseconds) [23:0] 00 062e 00 062f 00 0630 frequency lock fill rate [7:0] 00 0631 frequency lock drain rate [7:0] 00 profile 1 0632 priorities unused promoted prio rity [2:0] selection priority [2:0] 00 0633 reference period nominal period (femtoseconds) [47:0] (up to 1.125 sec) 00 0634 00 0635 00 0636 00 0637 00 0638 00 0639 unused nominal period [49:48] 00 063a tolerance inner tolerance (1 /tolerance) [15:0] (removes fault status; 10% down to 1 ppm) 00 063b 00 063c unused inner tolerance [19:16] 00 06cd outer tolerance (1/tolerance) [15:0] (indicates fault status; 10% down to 1 ppm) 00 063e 00 063f unused outer tolerance [19:16] 00 0640 validation validation timer (milliseconds) [15:0] (up to 65.5 sec) 00 0641 00
ad9548 rev. 0 | page 64 of 112 addr opt name d7 d6 d5 d4 d3 d2 d1 d0 def 0642 redetect timeout redetect timer (milliseconds) [15:0] (up to 65.5 sec) 00 0643 00 0644 digital loop filter coefficients alpha-0 linear [15:0] 00 0645 00 0646 alpha-2 exponent [1:0] alpha-1 exponent [5:0] 00 0647 beta-0 linear [6:0] alpha-2 exponent [2] 00 0648 beta-0 linear [14:7] 00 0649 unused beta-1 exponent [4:0] beta-0 linear [16:15] 00 064a gamma-0 linear [15:0] 00 064b 00 064c unused gamma-1 exponent [4:0] gamma-0 linear [16] 00 064d delta-0 linear [7:0] 00 064e delta-1 ex- ponent [0] delta-0 linear [14:8] 00 064f alpha-3 exponent [3:0] delta-1 exponent [4:1] 00 0650 frequency multiplica- tion r [23:0] 00 0651 00 0652 00 0653 unused r [29:24] 00 0654 s [23:0] 00 0655 00 0656 00 0657 unused s [29:24] 00 0658 v [7:0] 00 0659 u [3:0] unused v [9:8] 00 065a unused u [9:4] 00 065b lock detectors phase lock threshold (p icoseconds) [15:0] 00 065c 00 065d phase lock fill rate [7:0] 00 065e phase lock drain rate [7:0] 00 065f frequency lock threshol d (picoseconds) [23:0] 00 0660 00 0661 00 0662 frequency lock fill rate [7:0] 00 0663 frequency lock drain rate [7:0] 00 0664 to 067f unused profile 2 0680 priorities unused promoted prio rity [2:0] selection priority [2:0] 00 0681 reference period nominal period (femtoseconds) [47:0] (up to 1.125 sec) 00 0682 00 0683 00 0684 00 0685 00 0686 00 0687 unused nominal period [49:48] 00 0688 tolerance inner tolerance (1/tolerance) [15:0] (removes fault status; 10% down to 1 ppm) 00 0689 00 068a unused inner tolerance [19:16] 00 068b outer tolerance (1/tolerance) [15:0] (i ndicates fault status; 10% down to 1 ppm) 00 068c 00 068d unused outer tolerance [19:16] 00 068e validation validation timer (milliseconds) [15:0] (up to 65.5 sec) 00 068f 00
ad9548 rev. 0 | page 65 of 112 addr opt name d7 d6 d5 d4 d3 d2 d1 d0 def 0690 redetect timeout redetect timer (milliseconds) [15:0] (up to 65.5 seconds) 00 0691 00 0692 digital loop filter coefficients alpha-0 linear [15:0] 00 0693 00 0694 alpha-2 exponent [1:0] alpha-1 exponent [5:0] 00 0695 beta-0 linear [6:0] alpha-2 exponent [2] 00 0696 beta-0 linear [14:7] 00 0697 unused beta-1 exponent [4:0] beta-0 linear [16:15] 00 0698 gamma-0 linear [15:0] 00 0699 00 069a unused gamma-1 exponent [4:0] gamma-0 linear [16] 00 069b delta-0 linear [7:0] 00 069c delta-1 exponent [0] delta-0 linear [14:8] 00 069d alpha-3 exponent [3:0] delta-1 exponent [4:1] 00 069e frequency multiplica- tion r [23:0] 00 069f 00 06a0 00 06a1 unused r [29:24] 00 06a2 s [23:0] 00 06a3 00 06a4 00 06a5 unused s [29:24] 00 06a6 v [7:0] 00 06a7 u [3:0] unused v [9:8] 00 06a8 unused u [9:4] 00 06a9 lock detectors phase lock threshold (p icoseconds) [15:0] 00 06aa 00 06ab phase lock fill rate [7:0] 00 06ac phase lock drain rate [7:0] 00 06ad frequency lock threshol d (picoseconds) [23:0] 00 06ae 00 06af 00 06b0 frequency lock fill rate [7:0] 00 06b1 frequency lock drain rate [7:0] 00 profile 3 06b2 priorities unused promoted prio rity [2:0] selection priority [2:0] 00 06b3 reference period nominal period (femtoseconds) [47:0] (up to 1.125 sec) 00 06b4 00 06b5 00 06b6 00 06b7 00 06b8 00 06b9 unused nominal period [49:48] 00 06ba tolerance inner tolerance (1/tolerance) [15:0] (removes fault status; 10% down to 1 ppm) 00 06bb 00 06bc unused inner tolerance [19:16] 00 06bd outer tolerance (1/tolerance) [15:0] (indicates fault status; 10% down to 1 ppm) 00 06be 00 06bf unused outer tolerance [19:16] 00
ad9548 rev. 0 | page 66 of 112 addr opt name d7 d6 d5 d4 d3 d2 d1 d0 def 06c0 validation validation timer (milliseconds) [15:0] (up to 65.5 sec) 00 06c1 00 06c2 redetect timeout redetect timer (milliseconds) [15:0] (up to 65.5 sec) 00 06c3 00 06c4 digital loop filter coefficients alpha-0 linear [15:0] 00 06c5 00 06c6 alpha-2 exponent [1:0] alpha-1 exponent [5:0] 00 06c7 beta-0 linear [6:0] alpha-2 exponent [2] 00 06c8 beta-0 linear [14:7] 00 06c9 unused beta-1 exponent [4:0] beta-0 linear [16:15] 00 06ca gamma-0 linear [15:0] 00 06cb 00 06cc unused gamma-1 exponent [4:0] gamma-0 linear [16] 00 06cd delta-0 linear [7:0] 00 06ce delta-1 exponent [0] delta-0 linear [14:8] 00 06cf alpha-3 exponent [3:0] delta-1 exponent [4:1] 00 06d0 frequency multiplica- tion r [23:0] 00 06d1 00 06d2 00 06d3 unused r [29:24] 00 06d4 s [23:0] 00 06d5 00 06d6 00 06d7 unused s [29:24] 00 06d8 v [7:0] 00 06d9 u [3:0] unused v [9:8] 00 06da unused u [9:4] 00 06db lock detectors phase lock threshold (p icoseconds) [15:0] 00 06dc 00 06dd phase lock fill rate [7:0] 00 06de phase lock drain rate [7:0] 00 06df frequency lock threshol d (picoseconds) [23:0] 00 06e0 00 06e1 00 06e2 frequency lock fill rate [7:0] 00 06e3 frequency lock drain rate [7:0] 00 06e4- 06ff unused profile 4 through profile 7 0700- 07ff profile 4 through profile 7 the functionality of the profile 4 th rough profile 7 address locations (add ress 0700 to address 07ff) is identical to that of the profile 0 through profile 3 ad dress locations (address 0600 to address 06ff). operational controls 0a00 s general power-down reset sans regmap unused sysclk power- down reference power- down tdc power- down dac power- down dist power- down full power- down 00 0a01 c loop mode unused user holdover user freerun user selection mode [1:0] user reference selection [2:0] 00 0a02 s cal/sync unused sync distribu- tion calibrate system clock 00
ad9548 rev. 0 | page 67 of 112 addr opt name d7 d6 d5 d4 d3 d2 d1 d0 def 0a03 a, c resetfunc unused clear lf clear cci clear phase ac- cumulator reset auto sync reset tw history reset all irqs reset watchdog 00 0a04 a, c irq clearing unused sysclk unlocked sysclk locked unused unused sysclk cal complete sysclk cal started 00 0a05 a, c unused distribu- tion sync watchdog timer eeprom fault eeprom complete 00 0a06 a, c switching closed freerun holdover freq unlocked freq locked phase unlocked phase locked 00 0a07 a, c unused history updated freq un- clamped freq clamped phase slew unlimited phase slew limited 00 0a08 a, c ref aa new profile ref aa validated ref aa fault cleared ref aa fault ref a new profile ref a validated ref a fault cleared ref a fault 00 0a09 a, c ref bb new profile ref bb validated ref bb fault cleared ref bb fault ref b new profile ref b validated ref b fault cleared ref b fault 00 0a0a a, c ref cc new profile ref cc validated ref cc fault cleared ref cc fault ref c new profile ref c validated ref c fault cleared ref c fault 00 0a0b a, c ref dd new profile ref dd validated ref dd fault cleared ref dd fault ref d new profile ref d validated ref d fault cleared ref d fault 00 0a0c a, c incremental phase offset unused reset phase offset decrement phase offset increment phase offset 00 0a0d a, c reference profile detect detect dd detect d detect cc detect c de tect bb detect b detect aa detect a 00 0a0e a, c force validation timeout force timeout dd force timeout d force timeout cc force timeout c force timeout bb force timeout b force timeout aa force timeout a 00 0a0f c reference monitor override ref mon override dd ref mon override d ref mon override cc ref mon override c ref mon override bb ref mon override b ref mon override aa ref mon override a 00 0a10 c reference monitor bypass ref mon bypass dd ref mon bypass d ref mon bypass cc ref mon bypass c ref mon bypass bb ref mon bypass b ref mon bypass aa ref mon bypass a 00 status (read only; accessi ble during eeprom transactions) 0d00 r eeprom unused fault detected load in progress save in progress 0d01 r system clock unused stable unused unused cal in progress lock detected 0d02 r irq monitor unused sysclk unlocked sysclk locked unused unused sysclk cal complete sysclk cal started 0d03 r unused distribu- tion sync watchdog timer eeprom fault eeprom complete 0d04 r switching closed freerun holdover freq unlocked freq locked phase unlocked phase locked 0d05 r unused history updated freq un- clamped freq clamped phase slew unlimited phase slew limited 0d06 r ref aa new profile ref aa validated ref aa fault cleared ref aa fault ref a new profile ref a validated ref a fault cleared ref a fault 0d07 r ref bb new profile ref bb validated ref bb fault cleared ref bb fault ref b new profile ref b validated ref b fault cleared ref b fault 0d08 r ref cc new profile ref cc validated ref cc fault cleared ref cc fault ref c new profile ref c validated ref c fault cleared ref c fault 0d09 r ref dd new profile ref dd validated ref dd fault cleared ref dd fault ref d new profile ref d validated ref d fault cleared ref d fault 0d0a r, c dpll status offset slew limiting phase build-out freq lock phase lock loop switching holdover active free running 0d0b r, c frequency history active reference priority [3:0] active reference [3:0]
ad9548 rev. 0 | page 68 of 112 addr opt name d7 d6 d5 d4 d3 d2 d1 d0 def clamped available 0d0c r, c ref a profile selected selected profile [2:0] va lid fault fast slow 0d0d r, c ref aa profile selected selected profile [2:0] va lid fault fast slow 0d0e r, c ref b profile selected selected profile [2:0] va lid fault fast slow 0d0f r, c ref bb profile selected selected profile [2:0] va lid fault fast slow 0d10 r, c ref c profile selected selected profile [2:0] va lid fault fast slow 0d11 r, c ref cc profile selected selected profile [2:0] va lid fault fast slow 0d12 r. c ref d profile selected selected profile [2:0] va lid fault fast slow 0d13 r, c ref dd profile selected selected profile [2:0] va lid fault fast slow 0d14 r, c holdover history tuning word readback [47:0] 0d15 r, c 0d16 r, c 0d17 r, c 0d18 r, c 0d19 r, c nonvolatile memory (eeprom) control 0e00 write protect unused half rate mode write enable 00 0e01 e condition unused condition value [4:0] 00 0e02 a, e save unused save to eeprom 00 0e03 a, e load unused load from eeprom unused 00 eeprom storage sequence 0e10 e system clock data: 9 bytes 08 0e11 e address: 0x0100 01 0e12 e 00 0e13 e i/o update action: io_update 80 0e14 e sysclk calibrate action: calibrate system clock a0 0e15 e general data: 21 bytes 14 0e16 e address: 0x0200 02 0e17 e 00 0e18 e dpll data: 28 bytes 1b 0e19 e address: 0x0300 03 0e1a e 00 0e1b e clock distribution data: 26 bytes 19 0e1c e address: 0x0400 04 0e1d e 00 0e1e e i/o update action: io_update 80 0e1f e reference inputs data: 8 bytes 07 0e20 e address: 0x0500 05 0e21 e 00 0e22 e profile 0 and profile 1 data: 100 bytes 63 0e23 e address: 0x0600 06 0e24 e 00
ad9548 rev. 0 | page 69 of 112 addr opt name d7 d6 d5 d4 d3 d2 d1 d0 def 0e25 e profile 2 and profile 3 data: 100 bytes 63 0e26 e address: 0x0680 06 0e27 e 80 0e28 e profile 4 and profile 5 data: 100 bytes 63 0e29 e address: 0x0700 07 0e2a e 00 0e2b e profile 6 and profile 7 data: 100 bytes 63 0e2c e address: 0x0780 07 0e2d e 80 0e2e e i/o update action: io_update 80 0e2f e operational controls data: 17 bytes 10 0e30 e address: 0x0a00 0a 0e31 e 00 0e32 e i/o update action: io_update 80 0e33 e end of data action: end of data ff 0e34 to 0e3f e continuation of scratch pad area
ad9548 rev. 0 | page 70 of 112 register map bit descriptions serial port configuration (r egister 0000 to register 0005) table 36. serial configuration address bits bit name description 0000 [7] unidirectional select spi port sdo pin operating mode. 0 (default) = 3-wire. 1 = 4-wire (sdo pin enabled). [6] lsb first bit order for spi port. 0 (default) = most significant bit and byte first. 1 = least significant bit and byte first. [5] soft reset device reset (invokes an eeprom download if m[7:3] 0). 0 (default) = normal operation. 1 = reset. [4] long instruction 16-bit mode (the only mode supported by th e device). this bit is read only and reads back as logic 1. [0] unused table 37. reserved register address bits bit name description 0001 [7:0] unused table 38. silicon revision level (read-only) address bits bit name description 0002 [7:0] reserved default = 0x01 = 0b00000001 table 39. device id (read only) address bits bit name description 0003 [7:0] reserved default = 0x48 = 0b01001000 table 40. register readback control address bits bit name description 0004 [7:1] unused 0 read buffer register for buffered registers, serial port readback reads from actual (active) registers instead of from the buffer. 0 (default) = reads values currently applie d to the internal logic of the device. 1 = reads buffered values that take effect on the next assertion of the i/o update. table 41. soft i/o update address bits bit name description 0005 [7:1] unused 0 i/o update writing a 1 to this bit transfers the data in th e serial i/o buffer registers to the internal control registers of the device. this is an autoclearing bit.
ad9548 rev. 0 | page 71 of 112 system clock (register 0100 to register 0108) table 42. charge pump and lock detect control address bits bit name description 0100 [7] external loop filter enable enables use of an external sysclk pll loop filter 0 (default) = internal loop filter 1 = external loop filter [6] charge pump mode charge pump current control 0 (default) = automatic 1 = manual [5:3] charge pump current selects charge pump current when bit 6 = 1 000 = 125 a 001 = 250 a 010 = 375 a 011 (default) = 500 a 100 = 625 a 101 = 750 a 110 = 875 a 111 = 1000 a [2] lock detect timer disable enable the sysclk pll lock detect timer 0 (default) = enable 1 = disable [1:0] lock detect timer select lock detect timer depth 00 (default) = 128 01 = 256 10 = 512 11 = 1024 table 43. n divider address bits bit name description 0101 [7:0] n-divider system clock pll feedback divider value: 6 n 255 (default = 0x28 = 40) table 44. sysclk input options address bits bit name description 0102 [7] unused [6] m-divider reset reset the m-divider 0 = normal operation 1 (default) = reset when not using the m-divider, program this bit to logic 1. [5:4] m-divider system clock input divider 00 (default) = 1 01 = 2 10 = 4 11 = 8 [3] 2 frequency multiplier enable enable the 2 frequency multiplier 0 (default) = disable 1 = enable [2] pll enable enable the sysclk pll 0 = disable 1 (default) = enable [1:0] system clock source input mode select for sysclkx pins 00 = crystal resonator 01 (default) = low frequency clock source 10 = high frequency (direct) clock source 11 = input receiver power-down
ad9548 rev. 0 | page 72 of 112 table 45. nominal system clock (sysclk) period 1 address bits bit name description 0103 [7:0] system clock period (expressed in femtoseconds) system clock period, bits[7:0] 0104 [7:0] system clock period, bits[15:8] 0105 [7:5] unused [4:0] system clock period system clock period, bits[20:16] 1 units are femtoseconds. the default value is 0x0f424 = 1,000,000 (1 ns) an d implies a system cloc k frequency of 1 ghz. table 46. system clock stability period 1 address bits bit name description 0106 [7:0] system clock stability period system clock stability period, bits[7:0] (default = 0x01) 0107 [7:0] system clock stability peri od, bits[15:8] (default = 0x00) 0108 [7:4] unused [3:0] system clock stability period system clock stability period, bits[19:16] (default = 0x0) (default period = 0x00001, or 1 ms) 1 units are millisecon ds. the default value is 0x000001 = 1 (1 ms). general configuration (reg ister 0200 to register 0214) register 0200 to register 0207multifunction pin control (m0 to m7) table 47. multifunction pin (m0 to m7) control 1 address bits bit name description 0200 [7] m0 in/out in/out control for the m0 pin 0 (default) = input (control pin) 1 = output (status pin) [6:0] m0 function see table 24 and table 25 (default = 0xb0000000) 0201 [7] m1 in/out in/out control for the m1 pin (same as m0) [6:0] m1 function see table 24 and table 25 (default = 0xb0000000) 0202 [7] m2 in/out in/out control for the m2 pin (same as m0) [6:0] m2 function see table 24 and table 25 (default = 0xb0000000) 0203 [7] m3 in/out in/out control for the m3 pin (same as m0) [6:0] m3 function see table 24 and table 25 (default = 0xb0000000) 0204 [7] m4 in/out in/out control for the m4 pin (same as m0) [6:0] m4 function see table 24 and table 25 (default = 0xb0000000) 0205 [7] m5 in/out in/out control for the m5 pin (same as m0) [6:0] m5 function see table 24 and table 25 (default = 0xb0000000) 0206 [7] m6 in/out in/out control for the m6 pin (same as m0) [6:0] m6 function see table 24 and table 25 (default = 0xb0000000) 0207 [7] m7 in/out in/out control for the m7 pin (same as m0) [6:0] m7 function see table 24 and table 25 (default = 0xb0000000) 1 the default setting for all the multifunction pins is as an unused control input pin. table 48. irq pin output mode address bits bit name description 0208 [7:2] unused [1:0] irq pin output mode select the output mode of the irq pin 00 (default) = nmos, open drain (requires an external pull-up resistor) 01 = pmos, open drain (requires an external pull-down resistor) 10 = cmos, active high 11 = cmos, active low
ad9548 rev. 0 | page 73 of 112 register 0209 to register 0210irq mask the irq mask register bits form a one-to-one correspondence with the bits of the irq monitor register (address 0d02 to address 0d09). when set to logic 1, the irq mask bits enable the corresponding irq monitor bits to indicate an irq event. the default for all irq mask bits is logic 0, which prevents the irq monitor from detecting any internal interrupts. table 49. irq mask for sysclk address bits bit name description 0209 [7:6] unused [5] sysclk unlocked enables irq for indicating a sy sclk pll state transition from locked to unlocked [4] sysclk locked enables irq for indicating a sysc lk pll state transition from unlocked to locked [3:2] unused [1] sysclk cal complete enables irq for indicating that sysclk calibration has completed [0] sysclk cal started enables irq for indicating that sysclk calibration has begun table 50. irq mask for distribution sync, watchdog timer, and eeprom address bits bit name description 020a [7:4] unused [3] distribution sync enables irq for indicating a distribution sync event [2] watchdog timer enables irq for indica ting expiration of the watchdog timer [1] eeprom fault enables irq for indicating a faul t during an eeprom load or save operation [0] eeprom complete enables irq for indicating successful completion of an eeprom load or save operation table 51. irq mask for the digital pll address bits bit name description 020b [7] switching enables irq for indicating that the dpll is switching to a new reference [6] closed enables irq for indicating that the dpll has entered closed-loop operation [5] freerun enables irq for indicating that the dpll has entered free-run mode [4] holdover enables irq for indicating that the dpll has entered holdover mode [3] freq unlocked enables irq for indica ting that the dpll lost frequency lock [2] freq locked enables irq for indicating that the dpll has acquired frequency lock [1] phase unlocked enables irq for indi cating that the dpll lost phase lock [0] phase locked enables irq for indicating that the dpll has acquired phase lock table 52. irq mask for history update, frequency limit, and phase slew limit address bits bit name description 020c [7:5] unused [4] history updated enables irq for indicating th e occurrence of a tuning word history update [3] frequency unclamped enables irq for indicating a state transition frequency limiter from clamped to unclamped [2] frequency clamped enables irq for indicating a state transition of the frequency limiter from unclamped to clamped [1] phase slew unlimited enables irq for indicating a state transition of the phase slew limiter from slew limiting to not slew limiting [0] phase slew limited enables irq for indicating a state transition of the phase slew limiter from not slew limiting to slew limiting
ad9548 rev. 0 | page 74 of 112 table 53. irq mask for reference inputs address bits bit name description 020d [7] ref aa new profile enables irq for indicating that ref aa has switched to a new profile [6] ref aa validated enables irq for indicating that ref aa has been validated [5] ref aa fault cleared enables irq for indicating that ref aa has been clea red of a previous fault [4] ref aa fault enables irq for indi cating that ref aa has been faulted [3] ref a new profile enables irq for indicati ng that ref a has switched to a new profile [2] ref a validated enables irq for indicating that ref a has been validated [1] ref a fault cleared enables irq for indicating that ref a has been cleared of a previous fault [0] ref a fault enables irq for indica ting that ref a has been faulted 020e [7] ref bb new profile enables irq for indicati ng that ref bb has switched to a new profile [6] ref bb validated enables irq for indicating that ref bb has been validated [5] ref bb fault cleared enables irq for indicating that ref bb has been cleared of a previous fault [4] ref bb fault enables irq for indicating that ref bb has been faulted [3] ref b new profile enables irq for indicating that ref b has switched to a new profile [2] ref b validated enables irq for indicating that ref b has been validated [1] ref b fault cleared enables irq for indicating that ref b has been cleared of a previous fault [0] ref b fault enables irq for indicating that ref b has been faulted 020f [7] ref cc new profile enables irq for indicating that ref cc has switched to a new profile [6] ref cc validated enables irq for indicating that ref cc has been validated [5] ref cc fault cleared enables irq for indicating that ref cc has been cleared of a previous fault [4] ref cc fault enables irq for indicating that ref cc has been faulted [3] ref c new profile enables irq for indicating that ref c has switched to a new profile [2] ref c validated enables irq for indicating that ref c has been validated [1] ref c fault cleared enables irq for indicating that ref c has been cleared of a previous fault [0] ref c fault enables irq for indica ting that ref c has been faulted 0210 [7] ref dd new profile enables irq for indicating that ref dd has switched to a new profile [6] ref dd validated enables irq for indicating that ref dd has been validated [5] ref dd fault cleared enables irq for indicating that ref dd has been clea red of a previous fault [4] ref dd fault enables irq for indica ting that ref dd has been faulted [3] ref d new profile enables irq for indicating that ref d has switched to a new profile [2] ref d validated enables irq for indicating that ref d has been validated [1] ref d fault cleared enables irq for indicating that ref d has been cleared of a previous fault [0] ref d fault enables irq for indica ting that ref d has been faulted table 54. watchdog timer 1 address bits bit name description 0211 [7:0] watchdog timer watchdog t imer, bits[7:0] (default = 0x00) 0212 [7:0] watchdog timer, bi ts[15:8] (default = 0x00) 1 the watchdog timer is expressed in milliseconds. the default value is 0 (disabled). table 55. auxiliary dac 1 address bits bit name description 0213 [7:0] full-scale current full scale current, bits[7:0] (default = 0xff) 0214 [7] dac shutdown shut down the dac current sources. 0 (default) = normal operation 1 = shut down [6:2] unused [1:0] full-scale current full-scale current, bits[9:8] (default = 0b01) (default current = 0x1ff, or 20.1 ma) 1 the default dac full- scale current value is 0x01ff = 511, which equates to 20.1375 ma.
ad9548 rev. 0 | page 75 of 112 dpll configuration (register 0300 to register 031b) table 56. free running frequency tuning word 1 address bits bit name description 0300 [7:0] frequency (expressed as a 48-bit frequency tuning word) free running frequency tuning word, bits[7:0] 0301 [7:0] free running frequency tuning word, bits[15:8] 0302 [7:0] free running frequency tuning word, bits[23:9] 0303 [7:0] free running frequency tuning word, bits[31:24] 0304 [7:0] free running frequency tuning word, bits[39:32] 0305 [7:0] free running frequency tuning word, bits[47:40] 1 the default free running tuning word is 0x000000 = 0, which equates to 0 hz. table 57. update tw address bits bit name description 0306 [7:1] unused [0] update tw a logic 1 written to this bit transfers the free running frequency tuning word (register 0300 to register 0305) to the register imbedde d in the tuning word processing logic. note that it is not necessary to write the up date tw bit when the device is in free-run mode. this is an autoclearing bit. table 58. pull-in range lower limit 1 address bits bit name description 0307 [7:0] pull-in range lower limit (expressed as a 24-bit frequency tuning word) lower limit pull-in range, bits[7:0] 0308 [7:0] lower limit pull-in range, bits[15:8] 0309 [7:0] lower limit pull-in range, bits[23:9] 030a [7:0] pull-in range upper limit (expressed as a 24-bit frequency tuning word) upper limit pull-in range, bits[7:0] 030b [7:0] upper limit pull-in range, bits[15:8] 030c [7:0] upper limit pull-in range, bits[23:9] 1 the default pull-in range lower limit is 0 and the upper range limit is 0xffffff, which effectively spans the full output freq uency range of the dds. table 59. dds phase offset 1 address bits bit name description 030d [7:0] open-loop phase offset (expressed in /2 15 radians) dds phase offset, bits[7:0] 030e [7:0] dds phase offset, bits[15:8] 1 the default dds phase offset is 0. table 60. fixed closed-loop phase lock offset 1 address bits bit name description 030f [7:0] fixed phase lock offset (expressed in pico- seconds) fixed phase lock offset, bits[7:0] 0310 [7:0] fixed phase lock offset, bits[15:8] 0311 [7:0] fixed phase lock offset, bits[23:16] 0312 [7:0] fixed phase lock offset, bits[31:24] 0313 [7:0] fixed phase lock offset, bits[39:32] 1 the default fixed closed loop phase lock offset is 0.
ad9548 rev. 0 | page 76 of 112 table 61. incremental closed-loop phase lock offset step size 1 address bits bit name description 0314 [7:0] incremental phase lock offset step size (expressed in pico- seconds per step) incremental phase lock offset step size, bits[7:0] 0315 [7:0] incremental phase lock offset step size, bits[15:8] 1 the default incremental closed-l oop phase lock offset step size value is 0x03e8 = 1000 (1 ns). table 62. phase slew rate limit 1 address bits bit name description 0316 [7:0] phase slew limit (expressed in nano- seconds per second) phase slew rate limit, bits[7:0] 0317 [7:0] phase slew rate limit, bits[15:8] 1 the default phase slew rate limit is 0 (or disabled). table 63. history accumulation timer 1 address bits bit name description 0318 [7:0] history accumulation timer (expressed in milliseconds) history accumulation timer, bits[7:0] 0319 [7:0] history accumulation timer, bits[15:8] 031a [7:0] history accumulation timer, bits[23:16] 1 do not program a timer value of 0. the history accumulation time r default value is 0x007530 = 30,000 (30 sec). table 64. history mode address bits bit name description 031b [7:5] unused [4] single-sample fallback controls the holdover history. if tuning word history is not available for the reference that was active just prior to holdover, then 0 (default) = use the free running frequency tuning word register value. 1 = use the last tuning word from the dpll. [3] persistent history controls the holdover history initialization. when switching to a new reference 0 (default) = clear the tuning word history. 1 = retain the previous tuning word history. [2:0] incremental average history mode value from 0 to 7 (default = 0).
ad9548 rev. 0 | page 77 of 112 clock distribution output configur ation (register 0400 to register 0419) table 65. distribution settings 1 address bits bit name description 0400 [7:6] unused [5] external distribution resistor output current control for the clock distribution outputs 0 (default) = internal current setting resistor 1 = external current setting resistor [4] receiver mode clock di stribution receiver mode 0 (default) = normal operation 1 = high frequency mode (super-nyquist) [3] out3 power-down power-down clock distribution output out3 0 (default) = normal operation 1 = power-down [2] out2 power-down power-down clock distribution output out2 0 (default) = normal operation 1 = power-down [1] out1 power-down power-down clock distribution output out1 0 (default) = normal operation 1 = power-down [0] out0 power-down power-down clock distribution output out0 0 (default) = normal operation 1 = power-down 1 when bits[3:0] = 1111, the clock distribution output enters a deep sleep mode. table 66. distribution enable address bits bit name description 0401 [7:4] unused [3] out3 enable enable the out3 driver. 0 (default) = disable. 1 = enable. [2] out2 enable enable the out2 driver. 0 (default) = disable. 1 = enable. [1] out1 enable enable the out1 driver. 0 (default) = disable. 1 = enable. [0] out0 enable enable the out0 driver. 0 (default) = disable. 1 = enable.
ad9548 rev. 0 | page 78 of 112 table 67. distribution synchronization address bits bit name description 0402 [7:6] unused [5:4] sync source select the sync source for the clock distrib ution output channels. 00 (default) = direct. 01 = active reference. 10 = dpll feedback edge. 11 = reserved. [3] out3 sync mask mask the synchronous reset to the out3 divider. 0 (default) = unmasked 1 = masked. [2] out2 sync mask mask the synchronous reset to the out2 divider. 0 (default) = unmasked. 1 = masked. [1] out1 sync mask mask the synchronous reset to the out1 divider. 0 (default) = unmasked. 1 = masked. [0] out0 sync mask mask the synchronous reset to the out0 divider. 0 (default) = unmasked. 1 = masked. table 68. automatic synchronization address bits bit name description 0403 [7:2] unused [1:0] automatic sync mode autosync mode 00 (default) = disabled 01 = sync on dpll frequency lock 10 = sync on dpll phase lock 11 = reserved table 69. distribution channel modes address bits bit name description 0404 [7:6] unused [5] out0 cmos phase invert when the output mode is cmos, the bit in verts the relative phase between the two cmos output pins. otherwise, this bit is nonfunctional. 0 (default) = not inverted. 1 = inverted. [4] out0 polarity invert invert the polarity of out0. 0 (default) = not inverted. 1 = inverted. [3] out0 drive strength out0 output drive capability control. 0 (default) = cmos: low drive strength; lvds: 3.5 ma nominal. 1 = cmos: normal drive strength; lvds: 7 ma nominal. [2:0] out0 mode out0 operating mode select. 000 = cmos (both pins) 001 = cmos (positive pin), tristate (negative pin). 010 = tristate (positive pin), cmos (negative pin). 011 (default) = tristate (both pins). 100 = lvds. 101 = lvpecl. 110 = reserved. 111 = reserved.
ad9548 rev. 0 | page 79 of 112 address bits bit name description 0405 [7:6] unused [5] out1 cmos phase invert when the output mode is cmos, the bit in verts the relative phase between the two cmos output pins. otherwise, this bit is nonfunctional. 0 (default) = not inverted. 1 = inverted. [4] out1 polarity invert invert the polarity of out1. 0 (default) = not inverted. 1 = inverted. [3] out1 drive strength out1 output drive capability control. 0 (default) = cmos: low drive strength; lvds: 3.5 ma nominal. 1 = cmos: normal drive strength; lvds: 7 ma nominal. [2:0] out1 mode out1 operating mode select. 000 = cmos (both pins). 001 = cmos (positive pin), tristate (negative pin). 010 = tristate (positive pin), cmos (negative pin). 011 (default) = tristate (both pins). 100 = lvds. 101 = lvpecl. 110 = reserved. 111 = reserved. 0406 [7:6] unused [5] out2 cmos phase invert when the output mode is cmos, the bit in verts the relative phase between the two cmos output pins. otherwise, this bit is nonfunctional. 0 (default) = not inverted. 1 = inverted. [4] out2 polarity invert invert the polarity of out2. 0 (default) = not inverted. 1 = inverted. [3] out2 drive strength out2 output drive capability control. 0 (default) = cmos: low drive strength; lvds: 3.5 ma nominal. 1 = cmos: normal drive strength; lvds: 7 ma nominal. [2:0] out2 mode out2 operating mode select. 000 = cmos (both pins). 001 = cmos (positive pin), tristate (negative pin). 010 = tristate (positive pin), cmos (negative pin). 011 (default) = tristate (both pins). 100 = lvds. 101 = lvpecl. 110 = reserved. 111 = reserved.
ad9548 rev. 0 | page 80 of 112 address bits bit name description 0407 [7:6] unused [5] out3 cmos phase invert when the output mode is cmos, the bit in verts the relative phase between the two cmos output pins. otherwise, this bit is nonfunctional. 0 (default) = not inverted. 1 = inverted. [4] out3 polarity invert invert the polarity of out3. 0 (default) = not inverted. 1 = inverted. [3] out3 drive strength out3 output drive capability control. 0 (default) = cmos: low drive strength; lvds: 3.5 ma nominal. 1 = cmos: normal drive strength; lvds: 7 ma nominal. [2:0] out3 mode out3 operating mode select. 000 = cmos (both pins). 001 = cmos (positive pin), tristate (negative pin). 010 = tristate (positive pin), cmos (negative pin). 011 (default) = tristate (both pins). 100 = lvds. 101 = lvpecl. 110 = reserved. 111 = reserved. register 0408 to register 0417di stribution channel dividers table 70. q0 divider 1 address bits bit name description 0408 [7:0] q0 q0 divider, bits[7:0] 0409 [7:0] q0 divider, bits[15:8] 040a [7:0] q0 divider, bits[23:16] 040b [7:6] unused [5:0] q0 q0 divider, bits[29:24] 1 the default value is 0 (or divide by 1). table 71. q1 divider 1 address bits bit name description 040c [7:0] q1 q1 divider, bits[7:0] 040d [7:0] q1 divider, bits[15:8] 040e [7:0] q1 divider, bits[23:16] 040f [7:6] unused [5:0] q1 q1 divider, bits[29:24] 1 the default value is 0 (or divide by 1). table 72. q2 divider 1 address bits bit name description 0410 [7:0] q2 q2 divider, bits[7:0] 0411 [7:0] q2 divider, bits[15:8] 0412 [7:0] q2 divider, bits[23:16] 0413 [7:6] unused [5:0] q2 q2 divider, bits[29:24] 1 the default value is 0 (or divide by 1).
ad9548 rev. 0 | page 81 of 112 table 73. q3 divider 1 address bits bit name description 0414 [7:0] q3 q3 divider, bits[7:0] 0415 [7:0] q3 divider, bits[15:8] 0416 [7:0] q3 divider, bits[23:16] 0417 [7:6] unused [5:0] q3 q3 divider, bits[29:24] 1 the default value is 0 (or divide by 1). reference input conf iguration (register 0500 to register 0507) table 74. reference power-down when all bits are set, the reference receiver section enters a deep sleep mode. address bits bit name description 0500 [7] ref dd power-down ref dd input receiver power-down 0 (default) = normal operation 1 = power-down [6] ref d power-down ref d input receiver power-down 0 (default) = normal operation 1 = power-down [5] ref cc power-down ref cc input receiver power-down 0 (default) = normal operation 1 = power-down [4] ref c power-down ref c input receiver power-down 0 (default) = normal operation 1 = power-down [3] ref bb power-down ref bb input receiver power-down 0 (default) = normal operation 1 = power-down [2] ref b power-down ref b input receiver power-down 0 (default) = normal operation 1 = power-down [1] ref aa power-down ref aa input receiver power-down 0 (default) = normal operation 1 = power-down [0] ref a power-down ref a input receiver power-down 0 (default) = normal operation 1 = power-down
ad9548 rev. 0 | page 82 of 112 table 75. reference logic family address bits bit name description 0501 [7:6] ref bb logic family select the logic family for th e ref bb input receiver (ignored if bits[5:4] = 00) 00 (default) = disabled 01 = 1.2 v to 1.5 v cmos 10 = 1.8 v to 2.5 v cmos 11 = 3.0 v to 3.3 v cmos [5:4] ref b logic family select logic family for ref b input receiver. 00 (default) = differential (refb/ bb is positive/negative input) 01 = 1.2 v to 1.5 v cmos 10 = 1.8 v to 2.5 v cmos 11 = 3.0 v to 3.3 v cmos [3:2] ref aa logic family the same as register 0501, bits[7:6] but for ref aa [1:0] ref a logic family the same as register 0501, bits[5:4] but for ref a 0502 [7:6] ref dd logic family the same as register 0501, bits[7:6] but for ref dd [5:4] ref d logic family the same as register 0501, bits[5:4] but for ref d [3:2] ref cc logic family the same as register 0501, bits[7:6] but for ref cc [1:0] ref c logic family the same as register 0501, bits[5:4] but for ref c table 76. manual reference profile selection address bits bit name description 0503 [7] enable ref aa manual profile select manual or automatic reference profile assignment for ref aa 0 (default) = automatic 1 = manual [6:4] ref aa manual profile manual profile assignment 000 (default) = profile 0 001 = profile 1 010 = profile 2 011 = profile 3 100 = profile 4 101 = profile 5 110 = profile 6 111 = profile 7 [3] enable ref a manual profile same as register 0503, bit 7 but for ref a [2:0] ref a manual profile same as register 0503, bits[6:4] but for ref a 0504 [7] enable ref bb manual profile same as register 0503, bit 7 but for ref b [6:4] ref bb manual profile same as re gister 0503, bits[6:4] but for ref bb [3] enable ref b manual profile same as register 0503, bit 7 but for ref b [2:0] ref b manual profile same as register 0503, bits[6:4] but for ref b 0505 [7] enable ref cc manual profile same as register 0503, bit 7 but for ref cc [6:4] ref cc manual profile same as register 0503, bits[6:4] but for ref cc [3] enable ref c manual profile same as register 050, bit 7 but for ref c [2:0] ref c manual profile same as register 0503, bits[6:4] but for ref c 0506 [7] enable ref dd m manual profile same as register 0503, bit 7 but for ref dd [6:4] ref dd manual profile same as register 0503, bits[6:4] but for ref dd [3] enable ref d manual profile same as register 0503, bit 7 but for ref d [2:0] ref d manual profile same as register 0503, bits[6:4] but for ref d
ad9548 rev. 0 | page 83 of 112 table 77. phase build-out switching address bits bit name description 0507 [7:3] unused [2:0] phase master threshold priority threshold priority level (a value of 0 to 7, with 0 (default) being the highest priority level). references with a selection priority value lower than this value are treated as phase masters (see the profile registers (register 0600 to register 07ff) section for the selection priority value). profile registers (register 0600 to register 07ff) note that the default value of every bit is 0 for profile 0 to profile 7. register 0600 to register 0631profile 0 table 78. prioritiesprofile 0 address bits bit name description 0600 [7:6] unused [5:3] promoted priority user-assigned priority level (0 to 7) of the reference associated with profile 0 while that reference is the active reference. the numeric value of the promoted priority must be less than or equal to the numeric value of the selection priority. [2:0] selection priority user-assigned priority level (0 to 7) of th e reference associated with profile 0, which ranks that reference relative to the others. table 79. reference periodprofile 0 address bits bit name description 0601 [7:0] reference period (in femtoseconds) nominal reference period, bits[7:0] 0602 [7:0] nominal reference period, bits[15:8] 0603 [7:0] nominal reference period, bits[23:16] 0604 [7:0] nominal reference period, bits[31:24] 0605 [7:0] nominal reference period, bits[39:32] 0606 [7:0] nominal reference period, bits[47:40] 0607 [7:2] unused [1:0] reference period nominal reference period, bits[49:48] table 80. toleranceprofile 0 address bits bit name description 0608 [7:0] inner tolerance inner tolerance, bits[7:0] 0609 [7:0] inner tolerance, bits[15:8] 060a [7:4] unused [3:0] inner tolerance inner tolerance, bits[19:16] 060b [7:0] outer tolerance outer tolerance, bits[7:0] 060c [7:0] outer tolerance, bits[5:8] 060d [7:4] unused [3:0] outer tolerance outer tolerance, bits[19:16] table 81. validation timerprofile 0 address bits bit name description 060e [7:0] validation timer (in milliseconds) validation timer, bits[7:0] 060f [7:0] validation timer, bits[15:8] table 82. redetect timerprofile 0 address bits bit name description 0610 [7:0] redetect timer (in milliseconds) redetect timer, bits[7:0] 0611 [7:0] redetect timer, bits[15:8]
ad9548 rev. 0 | page 84 of 112 table 83. digital loop filt er coefficientsprofile 0 1 address bits bit name description 0612 [7:0] alpha-0 linear alpha-0 coefficient linear, bits[7:0] 0613 [7:0] alpha-0 coefficient linear, bits[15:8] 0614 [7:6] alpha-2 exponent alpha-2 coefficient exponent, bits[1:0] [5:0] alpha-1 exponent alpha-1 coefficient exponent, bits[5:0] 0615 [7:1] beta-0 linear beta-0 coefficient linear, bits[6:0] [0] alpha-2 exponent alpha-2 coefficient exponent, bit 2 0616 [7:0] beta-0 linear beta-0 coefficient linear, bits[14:7] 0617 [7] unused [6:2] beta-1 exponent beta-1 coefficient exponent, bits[4:0] [1:0] beta-0 linear beta-0 coefficient linear, bits[16:15] 0618 [7:0] gamma-0 linear gamma-0 coefficient linear, bits[7:0] 0619 [7:0] gamma -0 coefficient linear, bits[15:8] 061a [7:6] unused [5:1] gamma-1 exponent gamma-1 coefficient exponent, bits[4:0] [0] gamma-0 linear gamma-0 coefficient linear, bit 16 061b [7:0] delta-0 linear delta-0 coefficient linear, bits[7:0] 061c [7] delta-1 exponent delta-1 coefficient exponent, bit 0 [6:0] delta-0 linear delta-0 coefficient linear, bits[14:8] 061d [7:4] alpha-3 exponent alpha-3 coefficient exponent, bits[3:0] [3:0] delta-1 exponent delta-1 coefficient exponent, bits[4:1] 1 the digital loop filter coefficients (, , , and ) have the general form: x(2 y ), where x is the linear component and y is the exponential component of the coefficient. the value of the linear component (x) constitutes a fraction, where 0 x < 1. the exponential component (y) is an integer. see the calculating digital filter coefficients section for details. table 84. r-dividerprofile 0 1 address bits bit name description 061e [7:0] r r, bits[7:0] 061f [7:0] r, bits[15:8] 0620 [7:0] r, bits[23:16] 0621 [7:6] unused [5:0] r r, bits[29:24] 1 the value stored in the r-divider register yields an ac tual divide ratio of one mo re than the programmed value. table 85. s-dividerprofile 0 1 address bits bit name description 0622 [7:0] s s, bits[7:0] 0623 [7:0] s, bits[15:8] 0624 [7:0] s, bits[23:16] 0625 [7:6] unused [5:0] s s, bits[29:24] 1 the value stored in the s-divider register yi elds an actual divide ratio of one more than the programmed value. furthermore, t he value of s must be at least 7.
ad9548 rev. 0 | page 85 of 112 table 86. fractional feed back dividerprofile 0 address bits bit name description 0626 [7:0] v v, bits[7:0] 0627 [7:4] u u, bits[3:0] [3:2] unused [1:0] v v, bits[9:8] 0628 [7:6] unused [5:0] u u, bits[9:4] table 87. lock detectorsprofile 0 address bits bit name description 0629 [7:0] phase lock threshold (in picoseconds) phase lock threshold, bits[7:0] 062a [7:0] phase lock threshold, bits[15:8] 062b [7:0] phase lock fill rate phase lock fill rate, bits[7:0] 062c [7:0] phase lock drain rate phase lock drain rate, bits[7:0] 062d [7:0] frequency lock thresh- old (in picoseconds) frequency lock threshold, bits[7:0] 062e [7:0] frequency lock threshold, bits[15:8] 062f [7:0] frequency lock threshold, bits[23:16] 0630 [7:0] frequency lock fill rate frequency lock fill rate, bits[7:0] 0631 [7:0] frequency lock drain rate frequency lock drain rate, bits[7:0] register 0632 to register 067fprofile 1 table 88. prioritiesprofile 1 address bits bit name description 0632 [7:6] unused [5:3] promoted priority user-assigned priority level (0 to 7) of the reference associated with profile 1 while that reference is the active reference. the numeric value of the promoted priority must be less than or equal to the numeric value of the selection priority. [2:0] selection priority user-assigned priority level (0 to 7) of th e reference associated with profile 1, which ranks that reference relative to the others. table 89. reference periodprofile 1 address bits bit name description 0633 [7:0] reference period (in femtoseconds) nominal reference period, bits[7:0] 0634 [7:0] nominal reference period, bits[15:8] 0635 [7:0] nominal reference period, bits[23:16] 0636 [7:0] nominal reference period, bits[31:24] 0637 [7:0] nominal reference period, bits[39:32] 0638 [7:0] nominal reference period, bits[47:40] 0639 [7:2] unused [1:0] reference period nominal reference period, bits[49:48]
ad9548 rev. 0 | page 86 of 112 table 90. toleranceprofile 1 address bits bit name description 063a [7:0] inner tolerance inner tolerance, bits[7:0] 063b [7:0] inner tolerance, bits[15:8] 063c [7:4] unused [3:0] inner tolerance inner tolerance, bits[19:16] 063d [7:0] outer tolerance outer tolerance, bits[7:0] 063e [7:0] outer tolerance, bits[15:8] 063f [7:4] unused [3:0] outer tolerance outer tolerance, bits[19:16] table 91. validation timerprofile 1 address bits bit name description 0640 [7:0] validation timer (in milliseconds) validation timer, bits[7:0] 0641 [7:0] validation timer, bits[15:8] table 92. redetect timerprofile 1 address bits bit name description 0642 [7:0] redetect timer (in milliseconds) redetect timer, bits[7:0] 0643 [7:0] redetect timer, bits[15:8] table 93. digital loop filt er coefficientsprofile 1 1 address bits bit name description 0644 [7:0] alpha-0 linear alpha-0 coefficient linear, bits[7:0] 0645 [7:0] alpha-0 coefficient linear, bits[15:8] 0646 [7:6] alpha-2 exponent alpha-2 coefficient exponent, bits[1:0] [5:0] alpha-1 exponent alpha-1 coefficient exponent, bits[5:0] 0647 [7:1] beta -0 linear beta-0 coefficient linear, bits[6:0] [0] alpha-2 exponent alpha-2 coefficient exponent, bit 2 0648 [7:0] beta-0 linear beta-0 coefficient linear, bits[14:7] 0649 [7] unused [6:2] beta-1 exponent beta-1 coefficient exponent, bits[4:0] [1:0] beta-0 linear beta-0 coefficient linear, bits[16:15] 064a [7:0] gamma-0 linear gamma-0 coefficient linear, bits[7:0] 064b [7:0] gamma-0 coefficient linear, bits[15:8] 064c [7:6] unused [5:1] gamma-1 exponent gamma-1 coefficient exponent, bits[4:0] [0] gamma-0 linear gamma-0 coefficient linear, bit 16 064d [7:0] delta-0 linear delta-0 coefficient linear, bits[7:0] 064e [7] delta-1 exponent delta-1 coefficient exponent, bit 0 [6:0] delta-0 linear delta-0 coefficient linear, bits[14:8] 064f [7:4] alpha-3 exponent alpha-3 coefficient exponent, bits[3:0] [3:0] delta-1 exponent delta-1 coefficient exponent, bits[4:1] 1 the digital loop filter coefficients (, , , and ) have the general form: x(2 y ), where x is the linear component and y is the exponential component of the coefficient. the value of the linear component (x) constitutes a fraction, where 0 x < 1. the exponential component (y) is an integer. see the calculating digital filter coefficients section for details.
ad9548 rev. 0 | page 87 of 112 table 94. r-dividerprofile 1 1 address bits bit name description 0650 [7:0] r r, bits[7:0] 0651 [7:0] r, bits[15:8] 0652 [7:0] r, bits[23:16] 0653 [7:6] unused [5:0] r r, bits[29:24] 1 the value stored in the r-divider register yields an ac tual divide ratio of one mo re than the programmed value. table 95. s-dividerprofile 1 1 address bits bit name description 0654 [7:0] s s, bits[7:0] 0655 [7:0] s, bits[15:8] 0656 [7:0] s, bits[23:16] 0657 [7:6] unused [5:0] s s, bits[29:24] 1 the value stored in the s-divider register yi elds an actual divide ratio of one more than the programmed value. furthermore, t he value of s must be at least 7. table 96. fractional feed back dividerprofile 1 address bits bit name description 0658 [7:0] v v, bits[7:0] 0659 [7:4] u u, bits[3:0] [3:2] unused [1:0] v v, bits[9:8] 065a [7:6] unused [5:0] u u, bits[9:4] table 97. lock detectorsprofile 1 address bits bit name description 065b [7:0] phase lock threshold (in picoseconds) phase lock threshold, bits[7:0] 065c [7:0] phase lock threshold, bits[15:8] 065d [7:0] phase lock fill rate phase lock fill rate, bits[7:0] 065e [7:0] phase lock drain rate phase lock drain rate, bits[7:0] 065f [7:0] frequency lock threshold (in picoseconds) frequency lock threshold, bits[7:0] 0660 [7:0] frequency lock threshold, bits[15:8] 0661 [7:0] frequency lock threshold, bits[23:16] 0662 [7:0] frequency lock fill rate frequency lock fill rate, bits[7:0] 0663 [7:0] frequency lock drain rate frequency lock drain rate, bits[7:0] 0664 to 067f [7:0] unused register 0680 to register 06b1profile 2 table 98. prioritiesprofile 2 address bits bit name description 0680 [7:6] unused [5:3] promoted priority user-assigned priority level (0 to 7) of the reference associated with profile 2 while that reference is the active reference. the numeric value of the promoted priority must be less than or equal to the numeric value of the selection priority. [2:0] selection priority user-assigned priority level (0 to 7) of th e reference associated with profile 2, which ranks that reference relative to the others.
ad9548 rev. 0 | page 88 of 112 table 99. reference periodprofile 2 address bits bit name description 0681 [7:0] reference period (in femtoseconds) nominal reference period, bits[7:0] 0682 [7:0] nominal reference period, bits[15:8] 0683 [7:0] nominal reference period, bits[23:16] 0684 [7:0] nominal reference period, bits[31:24] 0685 [7:0] nominal reference period, bits[39:32] 0686 [7:0] nominal reference period, bits[47:40] 0687 [7:2] unused [1:0] reference period nominal reference period, bits[49:48] table 100. toleranceprofile 2 address bits bit name description 0688 [7:0] inner tolerance inner tolerance, bits[7:0] 0689 [7:0] inner tolerance, bits[15:8] 068a [7:4] unused [3:0] inner tolerance inner tolerance, bits[19:16] 068b [7:0] outer tolerance outer tolerance, bits[7:0] 068c [7:0] outer tolerance, bits[15:8] 068d [7:4] unused [3:0] outer tolerance outer tolerance, bits[19:16] table 101. validation timerprofile 2 address bits bit name description 068e [7:0] validation timer (in milliseconds) validation timer, bits[7:0] 068f [7:0] validation timer, bits[15:8] table 102. redetect timerprofile 2 address bits bit name description 0690 [7:0] redetect timer (in milliseconds) redetect timer, bits[7:0] 0691 [7:0] redetect timer, bits[15:8] table 103. digital loop filt er coefficientsprofile 2 1 address bits bit name description 0692 [7:0] alpha-0 linear alpha-0 coefficient linear, bits[7:0] 0693 [7:0] alpha-0 coefficient linear, bits[15:8] 0694 [7:6] alpha-2 exponent alpha-2 coefficient exponent, bits[1:0] [5:0] alpha-1 exponent alpha-1 coefficient exponent, bits[5:0] 0695 [7:1] beta-0 linear beta-0 coefficient linear, bits[6:0] [0] alpha-2 exponent alpha-2 coefficient exponent, bit 2 0696 [7:0] beta 0-linear beta-0 coefficient linear, bits[14:7] 0697 [7] unused [6:2] beta-1 exponent beta-1 coefficient exponent, bits[4:0] [1:0] beta-0 linear beta-0 coefficient linear, bits[16:15] 0698 [7:0] gamma-0 linear gamma-0 coefficient linear, bits[7:0] 0699 [7:0] gamma-0 coefficient linear, bits[15:8] 069a [7:6] unused [5:1] gamma-1 exponent gamma-1 coefficient exponent, bits[4:0] [0] gamma-0 linear gamma-0 coefficient linear, bit 6 069b [7:0] delta -0 linear delta-0 coefficient linear, bits[7:0]
ad9548 rev. 0 | page 89 of 112 address bits bit name description 069c [7] delta-1 exponent delta-1 coefficient exponent, bit 0 [6:0] delta-0 linear delta-0 coefficient linear, bits[14:8] 069d [7:4] alpha-3 exponent alpha-3 coefficient exponent, bits[3:0] [3:0] delta-1 exponent delta-1 coefficient exponent, bits[4:1] 1 the digital loop filter coefficients (, , , and ) have the general form: x(2 y ), where x is the linear component and y is the exponential component of the coefficient. the value of the linear component (x) constitutes a fraction, where 0 x < 1. the exponential component (y) is an integer. see the calculating digital filter coefficients section for details. table 104. r-dividerprofile 2 1 address bits bit name description 069e [7:0] r r, bits[7:0] 069f [7:0] r, bits[15:8] 06a0 [7:0] r, bits[23:16] 06a1 [7:6] unused [5:0] r r, bits[29:24] 1 the value stored in the r-divider register yields an ac tual divide ratio of one mo re than the programmed value. table 105. s-dividerprofile 2 1 address bits bit name description 06a2 [7:0] s s, bits[7:0] 06a3 [7:0] s, bits[15:8] 06a4 [7:0] s, bits[23:16] 06a5 [7:6] unused [5:0] s s, bits[29:24] 1 the value stored in the s-divider register yi elds an actual divide ratio of one more than the programmed value. furthermore, t he value of s must be at least 7. table 106. fractional feedback dividerprofile 2 address bits bit name description 06a6 [7:0] v v, bits[7:0] 06a7 [7:4] u u, bits[3:0] [3:2] unused [1:0] v v, bits[9:8] 06a8 [7:6] unused [5:0] u u, bits[9:4] table 107. lock detectorsprofile 2 address bits bit name description 06a9 [7:0] phase lock threshold (in picoseconds) phase lock threshold, bits[7:0] 06aa [7:0] phase lock threshold, bits[15:8] 06ab [7:0] phase lock fill rate phase lock fill rate, bits[7:0] 06ac [7:0] phase lock drain rate phase lock drain rate, bits[7:0] 06ad [7:0] frequency lock thresh- old (in picoseconds) frequency lock threshold, bits[7:0] 06ae [7:0] frequency lock threshold, bits[15:8] 06af [7:0] frequency lock threshold, bits[23:16] 06b0 [7:0] frequency lock fill rate frequency lock fill rate, bits[7:0] 06b1 [7:0] frequency lock drain rate frequency lock drain rate, bits[7:0]
ad9548 rev. 0 | page 90 of 112 register 06b2 to register 07ffprofile 3 table 108. prioritiesprofile 3 address bits bit name description 06b2 [7:6] unused [5:3] promoted priority user-assigned priority level (0 to 7) of the reference associated with profile 3 while that reference is the active reference. the numeric value of the promoted priority must be less than or equal to the numeric value of the selection priority. [2:0] selection priority user-assigned priority level (0 to 7) of th e reference associated with profile 3, which ranks that reference relative to the others. table 109. reference periodprofile 3 address bits bit name description 06b3 [7:0] reference period (in femtoseconds) nominal reference period, bits[7:0] 06b4 [7:0] nominal reference period, bits[15:8] 06b5 [7:0] nominal reference period, bits[23:16] 06b6 [7:0] nominal reference period, bits[31:24] 06b7 [7:0] nominal reference period, bits[39:32] 06b8 [7:0] nominal reference period, bits[47:40] 06b9 [7:2] unused [1:0] reference period nominal reference period, bits[49:48] table 110. toleranceprofile 3 address bits bit name description 06ba [7:0] inner tolerance inner tolerance, bits[7:0] 06bb [7:0] inner tolerance, bits[15:8] 06bc [7:4] unused [3:0] inner tolerance inner tolerance, bits[19:16] 06bd [7:0] outer tolerance outer tolerance, bits[7:0] 06be [7:0] outer tolerance, bits[15:8] 06bf [7:4] unused [3:0] outer tolerance outer tolerance, bits[19:16] table 111. validation timerprofile 3 address bits bit name description 06c0 [7:0] validation timer (in milliseconds) validation timer, bits[7:0] 06c1 [7:0] validation timer, bits[15:8] table 112. redetect timerprofile 3 address bits bit name description 06c2 [7:0] redetect timer (in milliseconds) redetect timer, bits[7:0] 06c3 [7:0] redetect timer, bits[15:8] table 113. digital loop filt er coefficientsprofile 3 1 address bits bit name description 06c4 [7:0] alpha-0 linear alpha-0 coefficient linear, bits[7:0] 06c5 [7:0] alpha-0 coefficient linear, bits[15:8] 06c6 [7:6] alpha-2 exponent alpha-2 coefficient exponent, bits[1:0] [5:0] alpha-1 exponent alpha-1 coefficient exponent, bits[5:0] 06c7 [7:1] beta-0 linear beta-0 coefficient linear, bits[6:0] [0] alpha-2 exponent alpha-2 coefficient exponent, bit 2 06c8 [7:0] beta-0 linear beta-0 coefficient linear, bits[14:7] 06c9 [7] unused [6:2] beta-1 exponent beta-1 coefficient exponent, bits[4:0] [1:0] beta-0 linear beta-0 coefficient linear, bits[16:15]
ad9548 rev. 0 | page 91 of 112 address bits bit name description 06ca [7:0] gamma-0 linear gamma-0 coefficient linear, bits[7:0] 06cb [7:0] gamma-0 coefficient linear, bits[15:8] 06cc [7:6] unused [5:1] gamma-1 exponent gamma-1 coefficient exponent, bits[4:0] [0] gamma-0 linear gamma-0 coefficient linear, bit 16 06cd [7:0] delta-0 linear delta-0 coefficient linear, bits[7:0] 06ce [7] delta-1 exponent delta-1 coefficient exponent, bit 0 [6:0] delta-0 linear delta-0 coefficient linear, bits[14:8] 06cf [7:4] alpha-3 exponent alpha-3 coefficient exponent, bits[3:0] [3:0] delta-1 exponent delta-1 coefficient exponent, bits[4:1] 1 the digital loop filter coefficients (, , , and ) have the general form: x(2 y ), where x is the linear component and y is the exponential component of the coefficient. the value of the linear component (x) constitutes a fraction, where 0 x < 1. the exponential component (y) is an integer. see the calculating digital filter coefficients section for details. table 114. r dividerprofile 3 1 address bits bit name description 06d0 [7:0] r r, bits[7:0] 06d1 [7:0] r, bits[15:8] 06d2 [7:0] r, bits[23:16] 06d3 [7:6] unused [5:0] r r, bits[29:24] 1 the value stored in the r-divider register yields an ac tual divide ratio of one mo re than the programmed value. table 115. s dividerprofile 3 1 address bits bit name description 06d4 [7:0] s s, bits[7:0] 06d5 [7:0] s, bits[15:8] 06d6 [7:0] s, bits[23:16] 06d7 [7:6] unused [5:0] s s, bits[29:24] 1 the value stored in the s-divider register yi elds an actual divide ratio of one more than the programmed value. furthermore, t he value of s must be at least 7. table 116. fractional feedback dividerprofile 3 address bits bit name description 06d8 [7:0] v v, bits[7:0] 06d9 [7:4] u u, bits[3:0] [3:2] unused [1:0] v v, bits[9:8] 06da [7:6] unused [5:0] u u, bits[9:4]
ad9548 rev. 0 | page 92 of 112 table 117. lock detectorsprofile 3 address bits bit name description 06db [7:0] phase lock threshold (in picoseconds) phase lock threshold, bits[7:0] 06dc [7:0] phase lock threshold, bits[15:8] 06dd [7:0] phase lock fill rate phase lock fill rate, bits[7:0] 06de [7:0] phase lock drain rate phase lock drain rate, bits[7:0] 06df [7:0] frequency lock thresh- old (in picoseconds) frequency lock threshold, bits[7:0] 06e0 [7:0] frequency lock threshold, bits[15:8] 06e1 [7:0] frequency lock threshold, bits[23:16] 06e2 [7:0] frequency lock fill rate frequency lock fill rate, bits[7:0] 06e3 [7:0] frequency lock drain rate frequency lock drain rate, bits[7:0] 06e4 to 06ff [7:0] unused register 0700 to register 07 ffprofile 4 to profile 7 profile 4 (register 0700 to register 0731) is identical to profile 0 (register 0600 to register0631). profile 5 (register 0732 to register 077f) is identical to profile 1 (register 0632 to register 067f). profile 6 (register 0780 to register 07b1) is identical to profile 2 (register 0680 to register 06b1). profile 7 (register 07b2 to register 07ff) is identical to profile 3 (register 06b2 to register 06ff). operational controls (regis ter 0a00 to register 0a10) table 118. general power-down address bits bit name description 0a00 [7] reset sans reg map reset internal hard ware but retain programmed register values. 0 (default) = normal operation. 1 = reset. [6] unused [5] sysclk power-down place sysclk input and pll in deep sleep mode. 0 (default) = normal operation. 1 = power-down. [4] reference power- down place reference clock inputs in deep sleep mode. 0 (default) = normal operation. 1 = power-down. [3] tdc power-down place the time-to-digital converter in deep sleep mode. 0 (default) = normal operation. 1 = power-down. [2] dac power-down place the dac in deep sleep mode. 0 (default) = normal operation. 1 = power-down. [1] dist power-down place the clock distribution outputs in deep sleep mode. 0 (default) = normal operation. 1 = power-down. [0] full power-down place the entire device in deep sleep mode. 0 (default) = normal operation. 1 = power-down.
ad9548 rev. 0 | page 93 of 112 table 119. loop mode address bits bit name description 0a01 [7] unused [6] user holdover force the device into holdover mode. 0 (default) = normal operation. 1 = force device into holdover mode. the device behaves as though all input references are faulted. [5] user freerun force the device into free-run mode. 0 (default) = normal operation. 1 = force device into free-run mode. the free running frequency tuning word register specifies the dds output frequency. note that, when the user freerun bit is se t, it overrides the user holdover bit. [4:3] user selection mode select the operating mode of the reference switching state machine. 00 (default) = automatic mode. the fully automatic priority-based algorithm selects the active reference (bits[2:0] are ignored). 01 = fallback mode. the active reference is the us er reference (bits[2:0]) as long as it is valid. otherwise, use the fully automatic prio rity-based algorithm to select the active reference. 10 = holdover mode. the active reference is the user reference (bits[2:0]) as long as it is valid. otherwise, enter holdover mode. 11 = manual mode. the active reference is always the user reference (bits[2:0]). when using manual mode, be sure that the referenc e declared as the user reference (bits[2:0]) is programmed for manual reference-to-profile assignment in the appropriate manual reference profile selection register (address 0503 to address 0506). [2:0] user reference selection input reference when user selection mode = 01, 10, or 11. 000 (default) = input reference a 001 = input reference aa 010 = input reference b 011 = input reference bb 100 = input reference c 101 = input reference cc 110 = input reference d 111 = input reference dd table 120. cal/sync address bits bit name description 0a02 [7:2] unused [1] sync distribution setting this bit (default = 0) initiates sync hronization of the clock distribution output. while this bit = 1, the clock distribution outp ut stalls. synchronization occurs on the 1 to 0 transition of this bit. [0] calibrate system clock setting this bit (default = 0) initiates an internal calibration of the sysclk pll (assuming it is enabled). the calibration routine au tomatically selects the proper vco frequency band and signal amplitude. the internal system clock stalls during the calibration procedure, disabling the device until the calibration is complete (a few milliseconds).
ad9548 rev. 0 | page 94 of 112 register 0a03resetfunc table 121. reset functions 1 address bits bit name description 0a03 [7] unused [6] clear lf setting this bit (default = 0) clears the digital loop filter (intended as a debug tool). [5] clear cci setting this bit (default = 0) clears the cci filter (intended as a debug tool). [4] clear phase accumulator setting this bit (default = 0) clears dds phase accumulator (not a recommended action). [3] reset auto sync setting this bit (default = 0) resets the automatic synchronization logic (see register 0403). [2] reset tw history setting this bit (default = 0) resets the tuning word history logic (part of holdover functionality). [1] reset all irqs setting this bit (default = 0) clears the en tire irq monitor register (register 0d02 to register 0d09). it is the equivalent of setting all the bits of the irq clearing register (register 0a04 to register 0a0b). [0] reset watchdog setting this bit (default = 0) resets the watchdog timer (see register 0211 to register 0212). if the timer had timed out, it simply st arts a new timing cycle. if the timer has not yet timed out, it restarts at time zero wi thout causing a timeout event. continuously resetting the watchdog timer at intervals less than its timeout period prevents the watchdog timer from generating a timeout event. 1 all bits in this register are autoclearing. register 0a04 to register 0a0birq clearing the irq clearing registers are identical in format to the irq monitor registers (address 0d02 to address 0d09). when set to log ic 1, an irq clearing bit resets the corresponding irq monitor bit, thereby canceling the interrupt request for the indicated event. the irq clearing register is an autoclearing register. table 122. irq clearing for sysclk address bits bit name description 0a04 [7:6] unused [5] sysclk unlocked clears sysclk unlocked irq [4] sysclk locked clears sysclk locked irq [3:2] unused [1] sysclk cal complete clears sysclk calibration complete irq [0] sysclk cal started clears sysclk calibration started irq table 123. irq clearing for distributi on sync, watchdog timer, and eeprom address bits bit name description 0a05 [7:4] unused [3] distribution sync clears distribution sync irq [2] watchdog timer clears watchdog timer irq [1] eeprom fault clears eeprom fault irq [0] eeprom complete clears eeprom complete irq table 124. irq clearing for the digital pll address bits bit name description 0a06 [7] switching clears switching irq [6] closed clears closed irq [5] freerun clears freerun irq [4] holdover clears holdover irq [3] freq unlocked clears frequency unlocked irq [2] freq locked clears frequency locked irq [1] phase unlocked clears phase unlocked irq [0] phase locked clears phase locked irq
ad9548 rev. 0 | page 95 of 112 table 125. irq clearing for history update , frequency limit, and phase slew limit address bits bit name description 0a07 [7:5] unused [4] history updated clears history updated irq [3] frequency unclamped clears frequency unclamped irq [2] frequency clamped clears frequency clamped irq [1] phase slew unlimited clea rs phase slew unlimited irq [0] phase slew limited clears phase slew limited irq table 126. irq clearing for reference inputs address bits bit name description 0a08 [7] ref aa new profile clears ref aa new profile irq [6] ref aa validated clears ref aa validated irq [5] ref aa fault cleared clea rs ref aa fault cleared irq [4] ref aa fault clea rs ref aa fault irq [3] ref a new profile clears ref a new profile irq [2] ref a validated clears ref a validated irq [1] ref a fault cleared clears ref a fault cleared irq [0] ref a fault clears ref a fault irq 0a09 [7] ref bb new profile clears ref bb new profile irq [6] ref bb validated clears ref bb validated irq [5] ref bb fault cleared clea rs ref bb fault cleared irq [4] ref bb fault clears ref bb fault irq [3] ref b new profile clears ref b new profile irq [2] ref b validated clears ref b validated irq [1] ref b fault cleared clears ref b fault cleared irq [0] ref b fault clears ref b fault irq 0a0a [7] ref cc new profile clears ref cc new profile irq [6] ref cc validated clears ref cc validated irq [5] ref cc fault cleared clears ref cc fault cleared irq [4] ref cc fault clears ref cc fault irq [3] ref c new profile clears ref c new profile irq [2] ref c validated clears ref c validated irq [1] ref c fault cleared clea rs ref c fault cleared irq [0] ref c fault clears ref c fault irq 0a0b [7] ref dd new profile clears ref dd new profile irq [6] ref dd validated clears ref dd validated irq [5] ref dd fault cleared clea rs ref dd fault cleared irq [4] ref dd fault clears ref dd fault irq [3] ref d new profile clears ref d new profile irq [2] ref d validated clears ref d validated irq [1] ref d fault cleared clea rs ref d fault cleared irq [0] ref d fault clears ref d fault irq
ad9548 rev. 0 | page 96 of 112 table 127. incremental phase offset control address bits bit name description 0a0c [7:3] unused [2] reset phase offset resets the incremental phase offset to 0. this is an autoclearing bit. [1] decr phase offset decrements the incremental phase offset by the amount specified in the incremental phase lock offset step size regist er (register 0314 to register 0315). this is an autoclearing bit. [0] incr phase offset increments the incremental phase offset by the amount specified in the incremental phase lock offset step size regist er (register 0314 to register 0315). this is an autoclearing bit. table 128. reference profile selection state machine startup 1 address bits bit name description 0a0d [7] detect dd setting this bit starts the pr ofile selection state machine for input reference dd. [6] detect d setting this bit starts the profil e selection state machine for input reference d. [5] detect cc setting this bit starts the profil e selection state machine for input reference cc. [4] detect c setting this bit starts the profil e selection state machine for input reference c. [3] detect bb setting this bit starts the profil e selection state machine for input reference bb. [2] detect b setting this bit starts the profil e selection state machine for input reference b. [1] detect aa setting this bit starts the profil e selection state machine for input reference aa. [0] detect a setting this bit starts the profil e selection state machine for input reference a. 1 all bits in this register are autoclearing. table 129. reference validation override controls 1 address bits bit name description 0a0e [7] force timeout dd setting this bit emulates a timeout of the validation timer for reference dd. this is an autoclearing bit. [6] force timeout d setting this bit emulates a t imeout of the validation timer for reference d. this is an autoclearing bit. [5] force timeout cc setting this bit emulates a timeout of the validation timer for reference cc. this is an autoclearing bit. [4] force timeout c setting this bit emulates a t imeout of the validation timer for reference c. this is an autoclearing bit. [3] force timeout bb setting this bit emulates a t imeout of the validation timer for reference bb. this is an autoclearing bit. [2] force timeout b setting this bit emulates a timeout of the validation timer for reference b. this is an autoclearing bit. [1] force timeout aa setting this bit emulates a t imeout of the validation timer for reference aa. this is an autoclearing bit. [0] force timeout a setting this bit emulates a t imeout of the validation timer for reference a. this is an autoclearing bit.
ad9548 rev. 0 | page 97 of 112 address bits bit name description 0a0f [7] ref mon override dd overrides the reference monitor ref fault si gnal for reference dd (default = 0, not overridden). [6] ref mon override d overrides the reference monitor ref fault signal for reference d (default = 0, not overridden). [5] ref mon override cc overrides the reference monitor ref fault si gnal for reference cc (default = 0, not overridden). [4] ref mon override c overrides the reference monitor ref fault signal for reference c (default = 0, not overridden). [3] ref mon override bb overrides the reference monitor ref fault si gnal for reference bb (default = 0, not overridden). [2] ref mon override b overrides the reference monitor ref fault signal for reference b (default = 0, not overridden). [1] ref mon override aa overrides the reference monitor ref fault signal for reference aa (default = 0, not overridden). [0] ref mon override a overrides the reference monitor ref fault signal for reference a (default = 0, not overridden). 0a10 [7] ref mon bypass dd bypasses the reference monitor for reference dd (default = 0, not bypassed). [6] ref mon bypass d bypasses the reference monitor for reference d (default = 0, not bypassed). [5] ref mon bypass cc bypasses the reference monitor for reference cc (default = 0, not bypassed). [4] ref mon bypass c bypasses the reference monitor for reference c (default = 0, not bypassed). [3] ref mon bypass bb bypasses the reference monitor for reference bb (default = 0, not bypassed). [2] ref mon bypass b bypasses the reference monitor for reference b (default = 0, not bypassed). [1] ref mon bypass aa bypasses the reference monitor for reference aa (default = 0, not bypassed). [0] ref mon bypass a bypasses the reference monitor for reference a (default = 0, not bypassed). 1 see figure 34 for details. status readback (registe r 0d00 to register 0d19) all bits in register 0d00 to register 0d19 are read only. table 130. eeprom status address bits bit name description 0d00 [7:3] unused [2] fault detected an error occurred while saving data to or loading data from the eeprom. [1] load in progress the control logic sets this bit while data is being read from the eeprom. [0] save in progress the control logic sets this bit while data is bein g written to the eeprom. table 131. sysclk status address bits bit name description 0d01 [7:5] unused [4] stable the control logic sets this bit when the devi ce considers the system clock to be stable (see the system clock stability timer section). [3:2] unused [1] cal in progress the control logic holds this bit se t while the system clock calibration is in progress. [0] lock detected indicates the status of the system clock pll. 0 = unlocked. 1 = locked (or the pll is disabled).
ad9548 rev. 0 | page 98 of 112 register 0d02 to register 0d09irq monitor if not masked via the irq mask register (address 0209 to address 0210), then the appropriate irq monitor bit is set to a logic 1 when the indicated event occurs. these bits can only be cleared via the irq clearing register (address 0a04 to address 0a0b), the reset all irqs bit (register 0a03, bit 1), or a device reset. table 132. irq monitor for sysclk address bits bit name description 0d02 [7:6] unused [5] sysclk unlocked indicates a sysclk pll st ate transition from locked to unlocked [4] sysclk locked indicates a sysclk pll st ate transition from unlocked to locked [3:2] unused [1] sysclk cal complete indicates that sysclk calibration has completed [0] sysclk cal started indicates that sysclk calibration has begun table 133. irq monitor for distribution sync, watchdog timer, and eeprom address bits bit name description 0d03 [7:4] unused [3] distribution sync indicates a distribution sync event [2] watchdog timer indicates expi ration of the watchdog timer [1] eeprom fault indicates a fault during an eeprom load or save operation [0] eeprom complete indicates successful comple tion of an eeprom load or save operation table 134. irq monitor for the digital pll address bits bit name description 0d04 [7] switching indicates that the dpll is switching to a new reference [6] closed indicates that the dpll has entered closed-loop operation [5] freerun indicates that the dpll has entered free-run mode [4] holdover indicates that the dpll has entered holdover mode [3] freq unlocked indicates that the dpll lost frequency lock [2] freq locked indicates that the dpll has acquired frequency lock [1] phase unlocked indicates that the dpll lost phase lock [0] phase locked indicates that the dpll has acquired phase lock table 135. irq monitor for history update, frequency limit, and phase slew limit address bits bit name description 0d05 [7:5] unused [4] history updated indicates the occurrence of a tuning word history update [3] freq unclamped indicates a frequency limiter state transition from clamped to unclamped [2] freq clamped indicates a frequency limiter state transition from unclamped to clamped [1] phase slew unlimited indicates a phase slew limiter state transition from slew limiting to not slew limiting [0] phase slew limited indicates a phase slew limiter stat e transition from not slew limiting to slew limiting table 136. irq monitor for reference inputs address bits bit name description 0d06 [7] ref aa new profile indicates that ref aa has switched to a new profile [6] ref aa validated indicates that ref aa has been validated [5] ref aa fault cleared indicates that re f aa has been cleared of a previous fault [4] ref aa fault indicates that ref aa has been faulted [3] ref a new profile indicates that ref a has switched to a new profile [2] ref a validated indicates that ref a has been validated [1] ref a fault cleared indicates that re f a has been cleared of a previous fault [0] ref a fault indicates that ref a has been faulted
ad9548 rev. 0 | page 99 of 112 address bits bit name description 0d07 [7] ref bb new profile indicates that ref bb has switched to a new profile [6] ref bb validated indicates that ref bb has been validated [5] ref bb fault cleared indicates that re f bb has been cleared of a previous fault [4] ref bb fault indicates that ref bb has been faulted [3] ref b new profile indicates that ref b has switched to a new profile [2] ref b validated indicates that ref b has been validated [1] ref b fault cleared indicates that re f b has been cleared of a previous fault [0] ref b fault indicates that ref b has been faulted 0d08 [7] ref cc new profile indicates that ref cc has switched to a new profile [6] ref cc validated indicates that ref cc has been validated [5] ref cc fault cleared indicates that re f cc has been cleared of a previous fault [4] ref cc fault indicates that ref cc has been faulted [3] ref c new profile indicates that ref c has switched to a new profile [2] ref c validated indicates that ref c has been validated [1] ref c fault cleared indicates that re f c has been cleared of a previous fault [0] ref c fault indicates that ref c has been faulted 0d09 [7] ref dd new profile indicates that ref dd has switched to a new profile [6] ref dd validated indicates that ref dd has been validated [5] ref dd fault cleared indicates that ref dd has been cleared of a previous fault [4] ref dd fault indicates that ref dd has been faulted [3] ref d new profile indicates that ref d has switched to a new profile [2] ref d validated indicates that ref d has been validated [1] ref d fault cleared indicates that re f d has been cleared of a previous fault [0] ref d fault indicates that ref d has been faulted table 137. dpll status address bits bit name description 0d0a [7] offset slew limiting the current closed-loop phase offset is rate limited. [6] phase build-out a phase build- out transition was made to the currently active reference. [5] freq lock the dpll has achieved frequency lock. [4] phase lock the dpll has achieved phase lock. [3] loop switching the dpll is in the process of a reference switchover. [2] holdover the dpll is in holdover mode. [1] active the dpll is active (that is, operating in a closed-loop condition) [0] free running the dpll is free running (that is, operating in an open-loop condition) 0d0b [7] frequency clamped the upper or lowe r frequency tuning word clamp is in effect. [6] history available there is sufficient tuning word history available for holdover operation. [5:3] active reference priority priority value of the currently active reference. 000 = highest priority. 111 = lowest priority. [2:0] active reference index of the currently active reference. 000 = reference a. 001 = reference aa. 010 = reference b. 011 = reference bb. 100 = reference c. 101 = reference cc. 110 = reference d. 111 = reference dd.
ad9548 rev. 0 | page 100 of 112 table 138. input reference status address bits bit name description 0d0c [7] profile selected the control logic sets this bit when it assigns ref a to one of the eight profiles. [6:4] selected profile the index (0 to 7) of the profile assigned to ref a. note that these bits are meaningless unless bit 7 = 1. [3] valid ref a is valid for use (it is unfa ulted and its validation timer has expired). [2] fault ref a is not valid for use. [1] fast if bit 7 = 1, then this bit indicates that the frequency of ref a is higher than allowed by its profile settings. if bit 7 = 0, then this bit indicates that the frequency of ref a is above the maximum input reference frequency supported by the device. [0] slow if bit 7 = 1, then this bit indicates that the frequency of ref a is lower than allowed by its profile settings. if bit 7 = 0, then this bit indicates that the frequency of ref a is below the minimum input reference frequency supported by the device. 0d0d [7:0] same as 0d0c but for ref aa instead of ref a. 0d0e [7:0] same as 0d0c but for ref b instead of ref a. 0d0f [7:0] same as 0d0c but for ref bb instead of ref a. 0d10 [7:0] same as 0d0c but for ref c instead of ref a. 0d11 [7:0] same as 0d0c but for ref cc instead of ref a. 0d12 [7:0] same as 0d0c but for ref d instead of ref a. 0d13 [7:0] same as 0d0c but for ref dd instead of ref a. table 139. holdover history 1 address bits bit name description 0d14 [7:0] holdover history tuning word readback, bits[7:0] 0d15 [7:0] tuning word readback, bits[15:8] 0d16 [7:0] tuning word readack, bits[23:9] 0d17 [7:0] tuning word readback, bits[31:24] 0d18 [7:0] tuning word readback, bits[39:32] 0d19 [7:0] tuning word readback, bits[47:40] 1 these registers contain the current 48-bi t dds frequency tuning word generated by the tuning word history logic. nonvolatile memory (eepro m) control (register 0e00 to register 0e03) table 140. eeprom control address bits bit name description 0e00 [7:2] unused [1] half rate mode eeprom serial communication rate. 0 (default) = 400 khz (normal). 1 = 200 khz. [0] write enable eeprom write enable/protect. 0 (default) = eeprom write protected. 1 = eeprom write enabled. 0e01 [7:5] unused [4:0] condition value when set to a nonzero value (default = 0), these bits establish the condition for eeprom downloads. 0e02 [7:1] unused 0 save to eeprom upload data to the eeprom based on th e eeprom storage sequence. this is an autoclearing bit. 0e03 [7:2] unused [1] load from eeprom download data from the eeprom. this is an autoclearing bit. [0] unused
ad9548 rev. 0 | page 101 of 112 eeprom storage sequence (register 0e10 to register 0e3f) the default settings of register 0e10 to register 0e33 embody a sample scratch pad instruction sequence. the following is a des cription of the register defaults under the assumption that the controller has been instructed to carry out an eeprom storage sequence. table 141. eeprom storage sequence for system clock settings address bits bit name description 0e10 [7:0] system clock the default value of this register is 0x08, which the controller interprets as a data instruction. its decimal value is 8, which tells the controller to transfer nine bytes of data (8 + 1) beginning at the address specified by the next two bytes. the controller stores 0x08 in the eeprom and incr ements the eeprom address pointer. 0e11 [7:0] system clock the default value of these two registers is 0x0100. note that register 0e11 and register 0e12 are the most significant and least significant bytes of the target address, respectively. because the previous register contains a data instruction, these two registers define a starting address (in this case, 0x0100). the controller stores 0x0100 in the eeprom and increments the eeprom pointer by 2. it then transfers nine bytes from the register map (beginning at addr ess 0x0100) to the eeprom and increments the eeprom address pointer by 10 (nine data bytes and one checksum byte). the nine bytes transferred correspond to the system clock parameters in the register map. 0e12 [7:0] 0e13 [7:0] i/o update the default value of this register is 0x80, which the controller interprets as an i/o update instruction. the controller stores 0x80 in the eeprom and increments the eeprom address pointer. table 142. eeprom storage sequence for system clock calibration address bits bit name description 0e14 [7:0] sysclk calibrate the default value of this register is 0xa0, wh ich the controller interprets as a calibrate instruction. the controller stores 0xa0 in the eeprom and increments the eeprom address pointer. table 143. eeprom storage sequence for general configuration settings address bits bit name description 0e15 [7:0] general the default value of this register is 0x14, which the controller interprets as a data instruction. its decimal value is 20, which tells the controller to transfer 21 bytes of data (20 + 1) beginning at the address specified by the next two bytes. the controller stores 0x14 in the eeprom and incr ements the eeprom address pointer. 0e16 [7:0] general the default value of these two registers is 0x0200. note that register 0e16 and register 0e17 are the most significant and least significant bytes of the target address, respectively. because the previous register contains a data instruction, these two registers define a starting address (in this case, 0x0200). the controller stores 0x0200 in the eeprom and increments the eeprom pointer by 2. it then transfers 21 bytes from the register map (beginning at address 0x0200) to the eeprom and increments the eeprom address pointer by 22 (21 data bytes and one checksum byte). the 21 bytes transferred correspond to the general configuration parameters in the register map. 0e17 [7:0] table 144. eeprom storage sequence for dpll settings address bits bit name description 0e18 [7:0] dpll the default value of this register is 0x1b, which the controller interprets as a data instruction. its decimal value is 27, which tells the controller to transfer 28 bytes of data (27 + 1) beginning at the address specified by the next two bytes. the controller stores 0x1b in the eeprom an d increments the eeprom address pointer. 0e19 [7:0] dpll the default value of these two registers is 0x0300. note that register 0e19 and register 0e1a are the most significant and least significant bytes of the target address, respectively. because the previous register contains a data instruction, these two registers define a starting address (in this case, 0x0300). the controller stores 0x0300 in the eeprom and increments the eeprom pointer by 2. it then transfers 28 bytes from the register map (beginning at addr ess 0x0300) to the eeprom and increments the eeprom address pointer by 29 (28 data bytes and one checksum byte). the 28 bytes transferred correspond to the dpll parameters in the register map. 0e1a [7:0]
ad9548 rev. 0 | page 102 of 112 table 145. eeprom storage sequence for clock distribution settings address bits bit name description 0e1b [7:0] clock distribution the default value of this register is 0x19, which the controller interprets as a data instruction. its decimal value is 25, which tells the controller to transfer 26 bytes of data (25 + 1) beginning at the address specified by the next two bytes. the controller stores 0x19 in the eeprom and incr ements the eeprom address pointer. 0e1c [7:0] clock distribution the default value of these two registers is 0x0400. note that register 0e1c and register 0e1d are the most significant and least significant bytes of the target address, respectively. because the previous register contains a data instruction, these two registers define a starting address (i n this case, 0x0400). the controller stores 0x0400 in the eeprom and increments the eeprom pointer by 2. it then transfers 26 bytes from the register map (beginning at address 0x0400) to the eeprom and increments the eeprom address pointer by 27 (26 data bytes and one checksum byte). the 26 bytes transferred correspond to the clock distribution parameters in the register map. 0e1d [7:0] 0e1e [7:0] i/o update the default value of this register is 0x80, which the controller interprets as an i/o update instruction. the controller stores 0x80 in the eeprom and increments the eeprom address pointer. table 146. eeprom storage sequence for reference input settings address bits bit name description 0e1f [7:0] reference inputs the default value of this register is 0x07, which the controller interprets as a data instruction. its decimal value is 7, which tells the controller to transfer eight bytes of data (7 + 1) beginning at the address specified by the next two bytes. the controller stores 0x07 in the eeprom and incr ements the eeprom address pointer. 0e20 [7:0] reference inputs the default value of these two registers is 0x0500. note that register 0e20 and register 0e21 are the most significant and least significant bytes of the target address, respectively. because the previous register contains a data instruction, these two registers define a starting address (in this case, 0x0500). the controller stores 0x0500 in the eeprom and increments the eeprom pointer by 2. it then transfers eight bytes from the register map (beginning at address 0x0500) to the eeprom and increments the eeprom address po inter by nine (eight data bytes and one checksum byte). the eight bytes transferred correspond to the reference inputs parameters in the register map. 0e21 [7:0] table 147. eeprom storage sequence for profile 0 and profile 1 settings address bits bit name description 0e22 [7:0] profile 0 and profile 1 the default value of this register is 0x63, which the controller interprets as a data instruction. its decimal value is 99, which this tells the controller to transfer 100 bytes of data (99 + 1) beginning at the address specified by the next two bytes. the controller stores 0x63 in the eeprom an d increments the eeprom address pointer. 0e23 [7:0] profile 0 and profile 1 the default value of these two registers is 0x0600. note that register 0e23 and register 0e24 are the most significant and least significant bytes of the target address, respectively. because the previous register contains a data instruction, these two registers define a starting address (in this case, 0x0600). the controller stores 0x0600 in the eeprom and increments the eeprom pointer by 2. it then transfers 100 bytes from the register map (beginning at address 0x0600) to the eeprom and increments the eeprom address pointer by 101 (100 data bytes and one checksum byte). the 99 bytes transferred correspond to the profile 0 and profile 1 parameters in the register map. 0e24 [7:0]
ad9548 rev. 0 | page 103 of 112 table 148. eeprom storage sequence for profile 2 and profile 3 settings address bits bit name description 0e25 [7:0] profile 2 and profile 3 the default value of this register is 0x63, which the controller interprets as a data instruction. its decimal value is 99, which te lls the controller to transfer 100 bytes of data (99 + 1) beginning at the address specified by the next two bytes. the controller stores 0x63 in the eeprom and incr ements the eeprom address pointer. 0e26 [7:0] profile 2 and profile 3 the default value of these two registers is 0x0680. note that register 0e26 and register 0e27 are the most significant and least significant bytes of the target address, respectively. because the previous register contains a data instruction, these two registers define a starting address (in this case, 0x0680). the controller stores 0x0680 in the eeprom and increments the eeprom pointer by 2. it then transfers 100 bytes from the register map (beginning at address 0x0680) to the eeprom and increments the eeprom address pointer by 101 (100 data bytes and one checksum byte). the 99 bytes transferred correspond to the profile 2 and profile 3 parameters in the register map. 0e27 [7:0] table 149. eeprom storage sequence for profile 4 and profile 5 settings address bits bit name description 0e28 [7:0] profile 4 and profile 5 the default value of this register is 0x63, which the controller interprets as a data instruction. its decimal value is 99, which this tells the controller to transfer 100 bytes of data (99 + 1) beginning at the address specified by the next two bytes. the controller stores 0x63 in the eeprom an d increments the eeprom address pointer. 0e29 [7:0] profile 4 and profile 5 the default value of these two registers is 0x0700. note that register 0e29 and register 0e2a are the most significant and least significant bytes of the target address, respectively. because the previous register contains a data instruction, these two registers define a starting address (in this case, 0x0700). the controller stores 0x0700 in the eeprom and increments the eeprom pointer by 2. it then transfers 100 bytes from the register map (beginning at address 0x0700) to the eeprom and increments the eeprom address pointer by 101 (100 data bytes and one checksum byte). the 99 bytes transferred correspond to the profile 4 and profile 5 parameters in the register map. 0e2a [7:0] table 150. eeprom storage sequence for profile 6 and profile 7 settings address bits bit name description 0e2b [7:0] profile 6 and profile 7 the default value of this register is 0x63, which the controller interprets as a data instruction. its decimal value is 99, which this tells the controller to transfer 100 bytes of data (99 + 1) beginning at the address specified by the next two bytes. the controller stores 0x63 in the eeprom an d increments the eeprom address pointer. 0e2c [7:0] profile 6 and profile 7 the default value of these two registers is 0x0780. note that register 0e2c and register 0e2c are the most significant and least significant bytes of the target address, respectively. because the previous register contains a data instruction, these two registers define a starting address (in this case, 0x0780). the controller stores 0x0780 in the eeprom and increments the eeprom pointer by 2. it then transfers 100 bytes from the register map (beginning at address 0x0780) to the eeprom and increments the eeprom address pointer by 101 (100 data bytes and one checksum byte). the 99 bytes transferred correspond to the profile 6 and profile 7 parameters in the register map. 0e2d [7:0] 0e2e [7:0] i/o update the default value of this register is 0x80, which the controller interprets as an i/o update instruction. the controller stores 0x80 in the eeprom and increments the eeprom address pointer.
ad9548 rev. 0 | page 104 of 112 table 151. eeprom storage sequence for operational control settings address bits bit name description 0e2f [7:0] operational controls the default value of this register is 0x10, which the controller interprets as a data instruction. its decimal value is 16, which this tells the controller to transfer 17 bytes of data (16 + 1) beginning at the address specified by the next two bytes. the controller stores 0x10 in the eeprom and incr ements the eeprom address pointer. 0e30 [7:0] operational controls the default value of these two registers is 0x0a00. note that register 0e30 and register 0e31 are the most significant and least significant bytes of the target address, respectively. because the previous register contains a data instruction, these two registers define a starting address (in this case, 0x0a00). the controller stores 0x0a00 in the eeprom and incremen ts the eeprom pointer by 2. it then transfers 17 bytes from the register map (beginning at address 0x0a00) to the eeprom and increments the eeprom address pointer by 18 (17 data bytes and one checksum byte). the 17 bytes transferred correspond to the operational controls parameters in the register map. 0e31 [7:0] 0e32 [7:0] i/o update the default value of this register is 0x80, which the controller interprets as an i/o update instruction. the controller stores 0x80 in the eeprom and increments the eeprom address pointer. table 152. eeprom storage sequence for end of data address bits bit name description 0e33 [7:0] end of data the default value of this register is 0xff, which the controller interprets as an end instruction. the controller stores this instruction in the eeprom, resets the eeprom address pointer, and enters an idle state. note that, if this were a pause rather than an end instruction, the controller actions would be the same except that the controller would not reset the eeprom address pointer.
ad9548 rev. 0 | page 105 of 112 power supply partitions the ad9548 features multiple power supplies, and their power consumption varies with the ad9548 configuration. this section provides information about which power supplies can be grouped together and how the power consumption of each block varies with frequency. the numbers quoted here are for comparison only. please refer to the specifications section for exact numbers. with each group, bypass capacitors of 1 f in parallel with 10 f should be used. upon applying power to the device, internal circuitry monitors the 1.8 v digital core supply and the 3.3 v digital i/o supply. when these supplies cross the desired threshold level, the device generates an internal 10 s reset pulse. this pulse does not appear on the reset pin. 3.3 v supplies the 3.3 v supply domain consists of two main partitions, digital (dvdd3) and analog (avdd3). take care to keep these two supply domains separate. furthermore, the avdd3 consists of two subdomains: the clock distribution output domain (pin 31, pin 37, pin 38, and pin 44) and the rest of the avdd3 supply connections. generally, these supply domains can be joined together. however, if an application requires 1.8 v cmos driver operation in the clock distribution output block, then provide one 1.8 v supply domain to power the clock distribution output block. each output driver has a dedicated supply pin, as shown in table 153 . table 153. output driver supply pins output driver supply pin out0 31 out1 37 out2 38 out3 44 1.8 v supplies the 1.8 v supply domain consists of two main partitions, digital (dvdd) and analog (avdd). these two supply domains must be kept separate.
ad9548 rev. 0 | page 106 of 112 thermal performance table 154. thermal parameters for the ad9548 88-lead lfcsp package symbol thermal characteristic using a jedec51-7 plus jedec51-5 2s2p test board 1 value 2 unit ja junction-to-ambient thermal resistance, 0.0 m/s airflow per jedec jesd51-2 (still air) 18 c/w jma junction-to-ambient thermal resistance, 1.0 m/s airflow per jedec jesd51-6 (moving air) 16 c/w jma junction-to-ambient thermal resistance, 2.5 m/s airflow per jedec jesd51-6 (moving air) 14 c/w jb junction-to-board thermal resistance, 1.0 m/sec airflow per jedec jesd51-8 (moving air) 9 c/w jc junction-to-case thermal resistance (die-to-h eat sink) per mil-std 883, method 1012.1 1.0 c/w jt junction-to-top-of-package characterization parameter, 0 m/sec airflow per jedec jesd51-2 (still air) 0.1 c/w 1 the exposed pad on the bottom of the package must be soldered to ground to achieve the specified thermal performance. 2 results are from simulations. the pcb is a jedec multilayer ty pe. thermal performance for actual applications requires careful inspection of the conditions in the application to determine if they are similar to those assumed in these calculations. the ad9548 is specified for a case temperature (t case ). to ensure that t case is not exceeded, an airflow source can be used. use the following equation to determine the junction temperature on the application pcb: t j = t case + ( jt pd ) where: t j is the junction temperature (c). t case is the case temperature (c) measured by the customer at the top center of the package. jt is the value as indicated in table 154. pd is the power dissipation (see the power dissipation section). va lu e s of ja are provided for package comparison and pcb design considerations. ja can be used for a first order approx- imation of t j by the equation t j = t a + ( ja pd ) where t a is the ambient temperature (c). va lu e s of jc are provided for package comparison and pcb design considerations when an external heat sink is required. va lu e s of jb are provided for package comparison and pcb design considerations.
ad9548 rev. 0 | page 107 of 112 calculating digital filter coefficients the digital loop filter coefficients ( , , , and (see figure 40 )) relate to the time constants (t 1 , t 2 , and t 3 ) associated with the equivalent analog circuit for a third order loop filter ( figure 66 ). r2 from charge pump to vco r3 c3 c1 c2 08022-042 figure 66. third order analog loop filter the design process begins by deciding on two design parameters related to the second order loop filter shown in figure 67 : the desired open-loop bandwidth ( f p ) and phase margin ( ) . r2 from charge pump to vco c1 c2 08022-043 figure 67. second order analog loop filter an analysis of the second order loop filter leads to its primary time constant, t 1 . it can be shown that t 1 is expressible in terms of f p and as )cos( )sin(1 ? p 1 t ? = where pp f = . an analysis of the third order loop filter leads to the definition of another time constant, t 3 . it can be shown that t 3 is expressible in terms of the desired amount of additional attenuation introduced by r 3 and c 3 at some specified frequency offset ( f offset ) from the pll output frequency. offset atten 3 t ? = where offset offset f = . note that atten is the desired excess attenuation in decibels. furthermore, atten and offset should be chosen so that p f t 5 1 3 with an expression for t 1 and t 3 , it is possible to define an adjusted open-loop bandwidth ( f c ) that is slightly less than f p . it can be shown that c (f c expressed as a radian frequency) is expressible in terms of t 1 , t 3 , and (phase margin) as () () () () [] ? ? ? ? ? ? ? ? ? + ++ + ++ + = 31 3131 3131 31 c tt tttt tttt tt it can also be shown that the adjusted open-loop bandwidth leads to t 2 (the secondary time constant of the second order loop filter) expressed as () 31c 2 tt t + = calculation of the digital loop filter coefficients requires a scaling constant, k (related to the system clock frequency, f s ), and the pll feedback divide ratio, d. s f k 33 2 125,578,517,30 = 1 ++= v u sd where s, u, and v are the integer and fractional feedback divider values that reside in the profile registers. keep in mind that the desired integer feedback divide ratio is one more than the stored value of s (hence, the +1 term in the equation for d in this equation). this leads to the digital filter coefficients given by () ( ) () () () 2c 3c 1c 1 2c t t t kt dt + + + = ? ? ? ? ? ? ? ? + ? = 21s ttf 1132 1s tf 32 ? = 3s tf 32 = calculation of the coefficient register values requires the application of some special functions described as follows: the if() function y = if( test_statement , true_value , false_value ) where test_statement is a conditional expression (for example, x < 3), true_value is what y equals if the conditional expression is true, and false_value is what y equals if the conditional expression is false. the round() function y = round( x )
ad9548 rev. 0 | page 108 of 112 if x is an integer, then y = x. otherwise, y is the nearest integer to x. for example, round(2.1) = 2, round(2.5) = 3, and round(?3.1) = ?3. the ceil() function y = ceil( x ) if x is an integer, then y = x. otherwise, y is the next integer to the right on the number line. for example, ceil(2.8) = 3, whereas ceil(?2.8) = ?2. the min() function y = min( x 0 , x 1 , ... x n ) where x 0 through x n is a list of real numbers, and the value of y is the number in the list that is the farthest to the left on the number line. the max() function y = max(x 0 , x 1 , ... x n ) where x 0 through x n is a list of real numbers, and the value of y is the number in the list that is the farthest to the right on the number line. the log 2 () function )2(ln )(ln )(log 2 x x = where ln() is the natural log function and x is a positive, nonzero number. assume that the coefficient calculations for , , , and yield the following results: 012735446.0 = 5 1098672.6 ? ?= 5 1050373.7 ? ?= 002015399.0 = these values are floating point numbers that must be quantized according to the bit widths of the linear and exponential components of the coefficients as they appear in the register map. note that the calculations that follow indicate a positive value for the register entries of and . the reason is that and , which are supposed to be negative values, are stored in the ad9548 registers as positive values. the ad9548 converts the stored values to negative numbers within its signal processing core. a detailed description of the register value computations for , , , and is contained in the calculation of the register values section to the calculation of the register values section. calculation of the register values the quantized coefficient consists of four components, 0 , 1 , 2 , and 3 according to 321 0 quantized ++? = 16 2 where 0 , 1 , 2 , and 3 are the register values. 2 provides front- end gain and 3 provides back-end gain, and 1 shifts the binary decimal point of 0 to the left to accommodate small values of . calculation of 1 is a two-step process, as follows: )0)),((logceil,1(if 2 ? < = w [ ] )0,),0max(,63min,1(if 1 w < = if gain is necessary (that is, > 1), then it is beneficial to apply most or all of it to the front-end gain ( 2 ) implying that the calculation of 2 is to be done before 3 . calculation of 2 is a three-step process that leads directly to the calculation of 3 . )0)),((logceil,1(if 2 > = x [ ] )0,),0max(,22min,1(if x y > = ),7,8(if 2 yy = )0,7,8(if 3 ? = yy calculation of 0 is a two-step process, as follows: )2(round 16 321 z ??+ = [ ] ),1max(,535,65min z 0 = using the example value of = 0.012735446 yields w = 6, so 1 = 6 x = 0 and y = 0, so 2 = 0 and 3 = 0 z = 53,416.332099584, so 0 = 53,416 this leads to the following quantized value, which is very close to the desired value of 0.012735446: 1 0127356682 .0253416 22 ?= ? quantized calculation of the register values the quantized coefficient consists of two components, 0 and 1 according to )17( 1 2 || +? =? 0 quantized where 0 and 1 are the register values. calculation of 1 is a two- step process that leads to the calculation of 0 , which is also a two- step process. ))((logceil 2 ?= x [ ] ),0max(,31min x 1 = )2(round 17 1 y + = [ ] ),1max(,071,131min y 0 = using the example value of ? = 6.98672 10 ?5 yields x = 13, so 1 = 13 y = 75,019.3347657728, so 0 = 75,019
ad9548 rev. 0 | page 109 of 112 calculation of the register values this leads to the following quantized value, which is very close to the desired value of 6.98672x10 ?5 : the quantized coefficient consists of two components, 0 and 1 , according to 5 30 10 986688823.62019,75 ? ? ?= quantized )15( 2 1 0 quantized ?? +? = calculation of the register values the quantized coefficient consists of two components, 0 and 1 according to where 0 and 1 are the register values. calculation of 1 is a two-step process that leads to the calculation of 0 , which is also a two-step process. )17( 2 1 0 quantized ?? +? =? ))((logceil 2 ? = x where 0 and 1 are the register values. calculation of 1 is a two- step process that leads to the calculation of 0 , which is also a two- step process. [ ] ),0max(,31min x 1 = )2(round 15 1 y + = ))((logceil 2 ?= x [ ] ),1max(,767,32min y 0 = [] ),0max(,31min x 1 = given the example value of = 0.002015399, the preceding formulas yield )2(round 17 1 y + = [] ),1max(,071,131min y 0 = x = 8, 1 = 8 y = 16,906.392174592, 0 = 16,906 using the example value of ? = 7.50373 10 ?5 yields this leads to the following quantized value, which is very close to the desired value of 0.002015399: x = 13, so 1 = 13 y = 80,570.6873700352, so 1 = 80,571 49 0020153522 .0216906 23 ?= ? quantized this leads to the following quantized value, which is very close to the desired value of 7.50373x10 ?5 : 5 30 10 503759116.7280571 ? ? ?= quantized
ad9548 rev. 0 | page 110 of 112 outline dimensions compliant to jedec standards mo-220-vrrd. 032209-a 11.75 bsc sq 12.00 bsc sq 1 22 66 45 23 44 88 67 0.50 0.40 0.30 0.30 0.23 0.18 10.50 ref 0.60 max 0.60 max 6.15 6.00 sq 5.85 0.50 bsc 0.20 ref 12 max 0.05 max 0.01 nom seating plane top view pin 1 indicator exposed pad bottom view 0.90 0.85 0.80 0.70 0.65 0.60 pin 1 indicator for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. figure 68. 88-lead lead frame chip scale package [lfcsp_vq] 12 mm 12 mm body, very thin quad (cp-88-2) dimensions shown in millimeters ordering guide model temperature range packag e description package option ad9548bcpz 1 ?40c to +85c 88-lead lead frame chip scale package [lfcsp_vq] cp-88-2 ad9548bcpz-reel7 1 ?40c to +85c 88-lead lead frame chip scale package [lfcsp_vq] cp-88-2 ad9548/pcbz 1 ?40c to +85c evalua tion board cp-88-2 1 z = rohs compliant part.
ad9548 rev. 0 | page 111 of 112 notes
ad9548 rev. 0 | page 112 of 112 notes ?2009 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d08022-0-5 /09(0)

▲Up To Search▲

Price & Availability of AD9548PCBZ

	To Download AD9548PCBZ Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .